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AD9500BP 数据表(PDF) 7 Page - Analog Devices |
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AD9500BP 数据表(HTML) 7 Page - Analog Devices |
7 / 11 page AD9500 –7– REV. D INSIDE THE AD9500 The heart of the AD9500 is the linear ramp generator. A trig- gering event at the input of the AD9500 initiates the ramp cycle. As the ramp voltage falls, it will eventually go below the thresh- old set up by the internal DAC (digital-to-analog converter). A comparator monitors both the linear ramp voltage and the DAC threshold level. The output of the comparator serves as the output for the AD9500, and the interval from the trigger until the output switches is the total delay time of the AD9500. The total delay through the AD9500 is made up of two compo- nents. The first is the full-scale programmed delay, tD (max), determined by RSET and CEXT. The second component of the total delay is the minimum propagation delay through the AD9500 (tPD). The full-scale delay is variable from 2.5 ns to greater than 1 ms. The internal DAC is capable of generating 256 separate programmed delays within the full-scale range (this gives 10 ps increments for a 2.5 ns full-scale setting). The actual programmed delay is directly related to both the digital control data (digital data to the internal DAC) and the RC time constant established by RSET and CEXT. The specific relationship is as follows: Total Delay = Minimum Propagation Delay + Programmed Delay = tPD + (digital value/256) RSET (CEXT + 10 pF) Figure 3. Typical Programmed Delay Ranges The internal DAC determines the programmed delay by way of the threshold level at its output. The LATCH ENABLE control for the onboard latch is active (latches) logic “HIGH.” In the logic “LOW” state, the latch is transparent, and the internal DAC will attempt to follow changes at the digital data inputs. Both the LATCH ENABLE control and the data inputs are TTL compatible. The internal DAC may be updated at any time, but full timing accuracy may not be attained unless trig- gering events are held off until after the DAC settling time (tDAC). Figure 4. Internal Timing Diagram On resetting, the ramp voltage held in the timing capacitor (CEXT + 10 pF) is discharged. The AD9500 discharges the bulk of the ramp voltage very quickly, but to maintain absolute accu- racy, subsequent triggering events should be held off until after the linear ramp settling time (tLRS). Applications which employ high frequency triggering at a constant rate will not be affected by the slight settling errors since they will be constant for fixed reset-to-trigger cycles. The RESET and TRIGGER inputs of the AD9500 are differen- tial and must be driven relative to one another. Accordingly, the TRIGGER and RESET inputs are ideally suited for analog or complementary input signals. Single-ended ECL input signals can be accommodated by using the ECL midpoint reference (ECLREF) to drive one side of the differential inputs. The output of the AD9500 consists of both Q and Q driver stages, as well as the Q R output which is used primarily for extending the output pulsewidth. In the most direct reset con- figuration, either the Q or the Q output is tied to the respective RESET input. This generates a delayed output pulse with a duration equal to the reset delay time (tRD) of approximately 6 ns. Note that the reset delay time (tRD) becomes extended for very small programmed delay settings. The duration of the output pulse can be extended by driving the reset inputs with the Q R output through an RC network (see “Extended Output Pulsewidth” application). Using the Q R output to drive the reset circuit avoids loading the Q or Q outputs. Values in the specification table are based on 5 ns FSR test conditions. Nearly all dynamic specifications degrade for longer full scales. For details of performance change, request the appli- cation note “Using Digitally Programmable Delay Generators.” |
类似零件编号 - AD9500BP |
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类似说明 - AD9500BP |
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