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AD9244BSTRL-40 数据表(PDF) 5 Page - Analog Devices

部件名 AD9244BSTRL-40
功能描述  14-Bit, 40/65 MSPS Monolithic A/D Converter
Download  36 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9244BSTRL-40 数据表(HTML) 5 Page - Analog Devices

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REV. A
AD9244
–5–
Test
AD9244BST-65
AD9244BST-40
Parameter
Temp
Level
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
VI
65
40
MHz
Minimum Conversion Rate
Full
V
500
500
kHz
Clock Period
1
Full
V
15.4
25
ns
Clock Pulsewidth High
2
Full
V
4
4
ns
Clock Pulsewidth Low
2
Full
V
4
4
ns
Clock Pulsewidth High
3
Full
V
6.9
11.3
ns
Clock Pulsewidth Low
3
Full
V
6.9
11.3
ns
DATA OUTPUT PARAMETERS
Output Delay (tPD)
4
Full
V
3.5
7
3.5
7
ns
Pipeline Delay (Latency)
Full
V
8
8
Clock Cycles
Aperture Delay (tA)
Full
V
1.5
1.5
ns
Aperture Uncertainty (Jitter)
Full
V
0.3
0.3
ps rms
Output Enable Delay
Full
V
15
15
ns
OUT-OF-RANGE RECOVERY TIME
Full
V
2
1
Clock Cycles
NOTES
1The clock period may be extended to 2
µs with no degradation in specified performance at 25°C.
2With duty cycle stabilizer enabled.
3With duty cycle stabilizer disabled.
4Measured from clock 50% transition to data 50% transition with 5 pF load on each output.
Specifications subject to change without notice
(AVDD = 5 V, DRVDD = 3 V, unless otherwise noted.)
SWITCHING SPECIFICATIONS
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
ANALOG
INPUT
CLOCK
DATA
OUT
tPD
tA
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
Figure 1. Input Timing


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