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AD9280ARSRL 数据表(PDF) 3 Page - Analog Devices |
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AD9280ARSRL 数据表(HTML) 3 Page - Analog Devices |
3 / 24 page Parameter Symbol Min Typ Max Units Condition DIGITAL INPUTS High Input Voltage VIH 2.4 V Low Input Voltage VIL 0.3 V DIGITAL OUTPUTS High-Z Leakage IOZ –10 +10 µA Output = GND to VDD Data Valid Delay tOD 25 ns CL = 20 pF Data Enable Delay tDEN 25 ns Data High-Z Delay tDHZ 13 ns LOGIC OUTPUT (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 µA) VOH +2.95 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.80 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.05 V LOGIC OUTPUT (with DRVDD = 5 V) High Level Output Voltage (IOH = 50 µA) VOH +4.5 V High Level Output Voltage (IOH = 0.5 mA) VOH +2.4 V Low Level Output Voltage (IOL = 1.6 mA) VOL +0.4 V Low Level Output Voltage (IOL = 50 µA) VOL +0.1 V CLOCKING Clock Pulsewidth High tCH 14.7 ns Clock Pulsewidth Low tCL 14.7 ns Pipeline Latency 3 Cycles CLAMP Clamp Error Voltage EOC ±60 ±80 mV CLAMPIN = +0.5 V to +2.0 V, RIN = 10 Ω Clamp Pulsewidth tCPW 2 µsC IN = 1 µF (Period = 63.5 µs) NOTES 1See Figures 1a and 1b. Specifications subject to change without notice. AD9280 REFTS REFBS MODE AVDD 10k 10k 0.4 VDD AD9280 REFTS REFBF MODE REFTF REFBS 4.2k a. b. Figure 1. Equivalent Input Load AD9280 –3– REV. D |
类似零件编号 - AD9280ARSRL |
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类似说明 - AD9280ARSRL |
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