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AD8327ARU Datasheet(数据表) 3 Page - Analog Devices

部件型号  AD8327ARU
说明  5 V CATV Line Driver Coarse Step Output Power Control
下载  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 

 
 3 page
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REV. 0
–3–
AD8327
LOGIC INPUTS (TTL/CMOS-Compatible Logic)
Parameter
Min
Typ
Max
Unit
Logic “1” Voltage
2.1
5.0
V
Logic “0” Voltage
0
0.8
V
Logic “1” Current (VINH = 5 V) CLK, SDATA, DATEN
020
nA
Logic “0” Current (VINL = 0 V) CLK, SDATA, DATEN
–600
–100
nA
Logic “1” Current (VINH = 5 V) TXEN
50
190
µA
Logic “0” Current (VINL = 0 V) TXEN
–250
–30
µA
Logic “1” Current (VINH = 5 V) SLEEP
50
190
µA
Logic “0” Current (VINL = 0 V) SLEEP
–250
–30
µA
TIMING REQUIREMENTS
Parameter
Min
Typ
Max
Unit
Clock Pulsewidth (tWH)
16.0
ns
Clock Period (tC)
32.0
ns
Setup Time SDATA vs. Clock (tDS)
5.0
ns
Setup Time
DATEN vs. Clock (t
ES)
15.0
ns
Hold Time SDATA vs. Clock (tDH)
5.0
ns
Hold Time
DATEN vs. Clock (t
EH)
3.0
ns
Input Rise and Fall Times, SDATA,
DATEN, Clock (t
R, tF)10
ns
t
ES
VALID DATA WORD G1
MSB. . . .LSB
GAIN TRANSFER (G1)
t
DS
t
EH
8 CLOCK
CYCLES
GAIN TRANSFER (G2)
t
OFF
t
GS
ANALOG
OUTPUT
SIGNAL AMPLITUDE (p-p)
TXEN
CLK
SDATA
DATEN
t
ON
tC
t
WH
VALID DATA WORD G2
Figure 2. Serial Interface Timing
VALID DATA BIT
MSB
MSB-1
MSB-2
t
DS
t
DH
SDATA
CLK
Figure 3. SDATA Timing
(Full Temperature Range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz unless otherwise noted.)
(
DATEN, CLK, SDATA, TXEN, SLEEP, V
CC = 5 V: Full Temperature Range)




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