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AD8322-EVAL 数据表(PDF) 7 Page - Analog Devices |
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AD8322-EVAL 数据表(HTML) 7 Page - Analog Devices |
7 / 16 page REV. 0 AD8322 –7– APPLICATIONS General Application The AD8322 is primarily intended for use as the upstream power amplifier (PA) in DOCSIS (Data Over Cable Service Interface Specifications) certified cable modems and CATV set-top boxes. Upstream data is modulated in QPSK or QAM format. This is done with DSP or a dedicated QPSK/QAM modulator. The amplifier receives its input signal from the QPSK/QAM modula- tor or from a DAC. In either case the signal must be low-pass filtered before being applied to the amplifier. Because the distance from the cable modem to the central office will vary with each subscriber, the AD8322 must be capable of varying its output power by applying gain or attenuation to ensure that all signals arriving at the central office are of the same amplitude. The upstream signal path contains components such as a transformer and diplexer that will result in some amount of power loss. There- fore, the amplifier must be capable of providing enough power into a 75 Ω load to overcome these losses without sacrificing the integrity of the output signal. Operational Description The AD8322 is composed of three analog functions in the power- up or forward mode. The input amplifier (preamp) can be used single-ended or differentially. If the input is used in the differen- tial configuration, it is imperative that the input signals be 180 degrees out of phase and of equal amplitudes. This will ensure the proper gain accuracy and harmonic performance. The preamp stage drives a DAC, which provides the bulk of the AD8322’s attenuation (7 bits or 42.14 dB). The signals in the preamp and DAC gain blocks are differential to improve the PSRR and linear- ity. A differential current is fed from the DAC into the output stage, which amplifies these currents to the appropriate levels necessary to drive a 75 Ω load. The output stage utilizes negative feedback to implement a differential 75 Ω output impedance. This eliminates the need for external matching resistors. SPI Programming and Gain Adjustment Gain programming of the AD8322 is accomplished using a serial peripheral interface (SPI) and three digital control lines, DATEN, SDATA, and CLK. To change the gain, eight bits of data are streamed into the serial shift register through the SDATA port. The SDATA load sequence begins with a falling edge on the DATEN pin, thus activating the CLK line. Although the CLK line is now activated, no change in gain is observed. With the CLK line activated, data on the SDATA line is clocked into the serial shift register, Most Significant Bit (MSB) first, on the rising edge of each CLK pulse. A rising edge on the DATEN line latches the contents of the shift register into the attenuator core resulting in a well-controlled change in the output signal level. The serial interface timing for the AD8322 is shown in Fig- ures 2 and 3. The programmable gain range of the AD8322 is –12.64 dB to +29.5 dB and scales 6.02 dB for each major carry. Because the AD8322 was characterized with a TOKO transformer, the stated gain values already take into account the losses asso- ciated with the transformer. Valid gain codes are the major carries from decimal 1–128 (decimal values 1, 2, 4, 8, 16, 32, 64, 128). The resulting gain for each code can be seen in Table I. Although the AD8322 is designed for use with the previous eight codes, the intermediate codes can be used. The gain transfer function is as follows: AV = 20 × LOG (0.2332 × CODE) for 1 ≤ CODE ≤ 128 AV = 29.5 dB for CODE ≥ 128 where AV is the gain in dB and CODE is the decimal equivalent of the 8-bit word. Figure 4 shows the gain characteristic for all possible values (except 0) in an 8-bit word. Code 0 may be used if more feedthrough isolation is required. It typically provides –85 dB of isolation across the 5 MHz to 65 MHz upstream band. GAIN CODE – Decimal 35 0 30 25 20 15 10 0 –5 –10 –15 –20 32 64 96 128 160 192 224 256 5 Figure 4. Gain vs. Gain Code Input Bias, Impedance, and Termination The VIN+ and VIN– inputs have a dc bias level of approximately VCC/2, therefore the input signal should be ac-coupled. The differential input impedance is approximately 235 Ω while the single-ended input impedance is 210 Ω. If the AD8322 is being operated in a single-ended input configuration with a desired input impedance of 75 Ω, the V IN+ and VIN– inputs should be terminated as shown in Figure 5. For input impedances other than 75 Ω, the value of R1 in Figure 5 can be calculated using the following equation: ZR IN = 1 210 ZIN = 75 AD8322 R1 = 118 Figure 5. Single-Ended Input Termination |
类似零件编号 - AD8322-EVAL |
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类似说明 - AD8322-EVAL |
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