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AD8303AN 数据表(PDF) 2 Page - Analog Devices |
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AD8303AN 数据表(HTML) 2 Page - Analog Devices |
2 / 16 page +3 V OPERATION Parameter Symbol Condition Min Typ1 Max Units STATIC PERFORMANCE Resolution 2 N 12 Bits Relative Accuracy 2 INL –2 ±1/2 +2 LSB Differential Nonlinearity 2 DNL Monotonic, TA = +25°C –3/4 ±1/4 +3/4 LSB Differential Nonlinearity 2 DNL Monotonic –1 ±1/2 +1 LSB Zero-Scale Error VZSE Data = 000H 1.25 +4.5 mV Full-Scale Voltage 3 VFS Data = FFFH 2 2.039 2.0475 2.056 Volts Full-Scale Tempco 3, 4 TCVFS 16 ppm/ °C ANALOG OUTPUTS Output Current IOUT Data = 800H, ∆VOUT < 3 mV ±3mA Output Resistance to GND ROUT Data = 000H 30 Ω Capacitive Load 4 CL No Oscillation 3 500 pF REFERENCE OUTPUT Output Voltage VREF Load > 1 M Ω 1V LOGIC INPUTS Logic Input Low Voltage VIL 0.6 V Logic Input High Voltage VIH 2.1 V Input Leakage Current IIL 10 µA Input Capacitance 4 CIL 10 pF INTERFACE TIMING SPECIFICATIONS 4, 5 Clock Width High tCH 40 ns Clock Width Low tCL 40 ns Load Pulse Width tLDW 40 ns Data Setup tDS 15 ns Data Hold tDH 15 ns Reset Pulse Width tRS 40 ns Load Setup tLD1 15 ns Load Hold tLD2 40 ns Select tCSS 40 ns Deselect tCSH 40 ns AC CHARACTERISTICS 4 Voltage Output Settling Time 6 t S To ±0.1% of Full Scale 4 µs Voltage Output Settling Time 6 t S To ±1 LSB of Final Value 14 µs Shutdown Recovery Time t DSR To ±0.1% of Full Scale 10 µs Output Slew Rate SR Data = 000 H to FFFH to 000H 2.0 V/ µs DAC Glitch Q 15 nV/s Digital Feedthrough Q 15 nV/s SUPPLY CHARACTERISTICS Power Supply Range VDD RANGE DNL < ± 1 LSB 2.7 5.5 V Shutdown Current IDD_SD SHDN = 0, No Load, VIL = 0 V, TA = +25°C 0.02 1 µA Supply Current 7 IDD VDD = 3 V, VIL = 0 V, No Load 2 3.2 mA Power Dissipation PDISS VDD = 3 V, VIL = 0 V, No Load 6 9.6 mW Power Supply Sensitivity PSS ∆V DD = ± 5% 0.001 0.004 %/% NOTES 1Typical readings represent the average value of room temperature operation. 21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 H, 001H) are excluded from the linearity error measurement. 3Includes internal voltage reference error. 4These parameters are guaranteed by design and not subject to production testing. 5All input control signals are specified with t R = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level of 1.6 V. 6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. 7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels. Specifications subject to change without notice. REV. 0 –2– AD8303–SPECIFICATIONS (@ VDD = +2.7 V to +3.6 V, –40 C ≤ T A ≤ +85 C, unless otherwise noted) |
类似零件编号 - AD8303AN |
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类似说明 - AD8303AN |
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