AD800/AD802

REV. B

–4–

The PLL must provide a clock signal which tracks this phase

modulation in order to accurately retime jittered data. In order

for the VCO output to have a phase modulation which tracks

the input jitter, some modulation signal must be generated at

the output of the phase detector (see Figure 21). The

modulation output from the phase detector can only be

produced by a phase error between the data input and the clock

input. Hence, the PLL can never perfectly track jittered data.

However, the magnitude of the phase error depends on the gain

around the loop. At low frequencies the integrator provides very

high gain, and thus very large jitter can be tracked with small

phase errors between input data and recovered clock. At

frequencies closer to the loop bandwidth, the gain of the

integrator is much smaller, and thus less input jitter can be

tolerated. The PLL data output will have a bit error rate less

than 1

10

specified jitter applied to it.

Jitter Transfer

The PLL exhibits a low-pass filter response to jitter applied to

its input data.

Bandwidth

This describes the frequency at which the PLL attenuates

sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the PLL in dB.

Damping Factor,

step. A greater value of

PLL response to a phase step.

order feedback systems.

Acquisition Time

This is the transient time, measured in bit periods, required for

the PLL to lock on input data from its free-running state.

Symmetry

Symmetry is calculated as (100

on time)/period, where on

time equals the time that the clock signal is greater than the

midpoint between its “0” level and its “1” level.

Bit Error Rate vs. Signal-to-Noise Ratio

The AD800 and AD802 were designed to operate with standard

ECL signal levels at the data input. Although not recom-

mended, smaller input signals are tolerable. Figure 8, 14, and

20 show the bit error rate performance versus input signal-to-

noise ratio for input signal amplitudes of full 900 mV ECL, and

decreased amplitudes of 80 mV and 20 mV. Wideband ampli-

tude noise is summed with the data signals as shown in Figure

2. The full ECL and 80 mV signals give virtually indistinguish-

able results. The 20 mV signals also provide adequate perfor-

mance when in lock, but signal acquisition may be impaired.

∑

POWER

COMBINER

∑

0.47

µF

50

Ω

50

Ω

0.47

µF

POWER

COMBINER

75

Ω

1.0

µF

180

Ω

POWER

SPLITTER

FILTER

NOISE

SOURCE

100MHz – AD802-155

33MHz – AD800-52

GND

–5.2V

D.U.T.

AD800/AD802

DATA IN

DATA IN

DIFFERENTIAL

SIGNAL

SOURCE

Figure 2. Bit Error Rate vs. Signal-to-Noise Ratio Test:

Block Diagram

USING THE AD800 AND THE AD802 SERIES

Ground Planes

Use of one ground plane for connections to both analog and

digital grounds is recommended. Output signal sensitivity to

power supply noise (PECL configuration, Figure 22) is less

using one ground plane than when using separate analog and

digital ground planes.

Power Supply Connections

Use of a 10

µF tantalum capacitor between V

recommended.

Use of 0.1

µF ceramic capacitors between IC power supply or

substrate pins and ground is recommended. Power supply

decoupling should take place as close to the IC as possible.

Refer to schematics, Figure 22 and Figure 26, for advised

connections.

Sensitivity of IC output signals (PECL configuration,

Figure 22) to high frequency power supply noise (at 2

the

nominal data rate) can be reduced through the connection of

The type of bypass network to consider depends on the noise

tolerance required. The more complex bypass network schemes

tolerate greater power supply noise levels. Refer to Figures 23

and 24 for bypassing schemes and power supply sensitivity

curves.

Transmission Lines

Use of 50

Ω transmission lines are recommended for DATAIN,

CLKOUT, DATAOUT, and FRAC signals.

Terminations

Termination resistors should be used for DATAIN, CLKOUT,

DATAOUT, and FRAC signals. Metal, thick film, 1% tolerance

resistors are recommended. Termination resistors for the

DATAIN signals should be placed as close as possible to the

DATAIN pins.

OUT, FRAC, and CLKOUT signals should be individual, not

daisy chained. This will avoid crosstalk on these signals.

A ceramic capacitor may be used for the loop damping

capacitor.

Input Buffer

Use of an input buffer, such as a 10H116 Line Receiver IC, is

suggested for an application where the DATAIN signals do not

come directly from an ECL gate, or where noise immunity on

the DATAIN signals is an issue.