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AD7872 数据表(PDF) 4 Page - Analog Devices |
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AD7872 数据表(HTML) 4 Page - Analog Devices |
4 / 16 page AD7871/AD7872 –4– REV. D AD7871 PIN FUNCTION DESCRIPTION DIP No. Mnemonic Function 1 CONVST Convert Start. A low to high transition on this input puts the track/hold into the hold mode. This input is asynchronous to the CLK. CS and RD must be held high for the duration of this pulse. 2 CS Chip Select. Active low logic input. The device is selected when this input is active. With CONVST tied low, a new conversion is initiated when CS goes low. 3 RD Read. Active low logic input. This input is used in conjunction with CS low to enable the data outputs. 4 BUSY/INT Busy/Interrupt. Logic low output indicating converter status. See timing diagrams. 5 CLK Clock Input. An external TTL-compatible clock may be applied to this input. Alternatively, tying this pin to VSS enables the internal laser-trimmed oscillator. 6 DB13/HBEN Data Bit 13 (MSB)/High Byte Enable. The function of this pin is dependent on the state of the 14/ 8/CLK input (see Pin 28). When 14-bit data is selected, this pin provides the DB13 output. When either byte or serial data is selected, this pin becomes the HBEN logic input. HBEN is used for 8-bit bus interfacing. When HBEN is low, DB7 to DB0 is the lower byte of data. With HBEN high, DB7 to DB0 is the upper byte of data (see Table I). Table I. Byte Output Format HBEN DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 HIGH LOW LOW DB13 DB12 DB11 DB10 DB9 DB8 LOW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 7 DB12/ SSTRB Data Bit 12/Serial Strobe. When 14-bit data is selected, this pin provides the DB12 data output. Otherwise it is an active low three-state output that provides a framing pulse for serial data. 8 DB11/SCLK Data Bit 11/Serial Clock. When 14-bit data is selected, this pin provides the DB11 data output. Otherwise SCLK is the gated serial clock output that is derived from the internal or external ADC clock. If the 14/ 8/CLK input is held at –5 V, then the SCLK runs continuously. With 14/8/CLK at 0 V, it is gated off (three-state) after serial transmission is complete. 9 DB10/SDATA Data Bit 10/Serial Data. When 14-bit parallel data is selected, this pin provides the DB10 data output. Otherwise it is the three-state serial data output used in conjunction with SCLK and SSTRB in serial data transmission. Serial data is valid on the falling edge of SCLK, when SSTRB is low. 10–13 DB9–DB6 Three-State Data Outputs controlled by CS and RD. Their function depends on the state of the 14/ 8/CLK and the HBEN inputs. With 14/8/CLK high, they are always DB9–DB6; with 14/8/CLK low, their function depends on HBEN (see Table I). 14 DGND Digital Ground. Ground return for digital circuitry. 15–20 DB5/DB13– Three-State Data Outputs controlled by CS and RD. Their function depends on the 14/8/CLK DB0/DB8 and HBEN inputs. With 14/ 8/CLK high, they are always DB5–DB0; with 14/8/CLK low or –5 V, their function is controlled by HBEN (see Table I). 21 VDD Positive Supply, +5 V ± 5%. 22 AGND Analog Ground. Ground reference for analog circuitry. 23 CREF Decoupling point for on-chip reference. Connect 10 nF between this pin and AGND. 24 NC No Connect. 25 REF OUT Voltage Reference Output. The internal 3 V reference is provided at this pin. The external load capability is 500 µA. 26 VIN Analog Input. The input range is ±3 V. 27 VSS Negative Supply, –5 V ± 5%. 28 14/ 8/CLK Three-Function Input. Defines both the parallel and serial data formats. With this pin at +5 V, the output data is 14-bit parallel only. With this pin at 0 V, both byte and serial data are available, and the SCLK is noncontinuous. With this pin at –5 V, both byte and serial data are available and the SCLK is continuous. |
类似零件编号 - AD7872 |
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类似说明 - AD7872 |
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