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AD7856ARS 数据表(PDF) 11 Page - Analog Devices |
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AD7856ARS 数据表(HTML) 11 Page - Analog Devices |
11 / 32 page AD7856 –11– REV. A Table III. Channel Selection SGL/DIFF CH2 CH1 CH0 AIN(+)* AIN(–)* 0 000AIN1 AIN2 0 001AIN3 AIN4 0 010AIN5 AIN6 0 011AIN7 AIN8 0 100AIN2 AIN1 0 101AIN4 AIN3 0 110AIN6 AIN5 0 111AIN8 AIN7 1 000AIN1 AGND 1 001AIN3 AGND 1 010AIN5 AGND 1 011AIN7 AGND 1 100AIN2 AGND 1 101AIN4 AGND 1 110AIN6 AGND 1 111AIN8 AGND *AIN(+) refers to the positive input seen by the AD7856 sample and hold circuit. AIN(–) refers to the negative input seen by the AD7856 sample and hold circuit. Table IV. Calibration Selection CALMD CALSLT1 CALSLT0 Calibration Type 0 0 0 A Full Internal Calibration is initiated where the Internal DAC is calibrated followed by the Internal Gain Error, and finally the Internal Offset Error is calibrated out. This is the default setting. 0 0 1 Here the Internal Gain Error is calibrated out followed by the Internal Offset Error calibrated out. 0 1 0 This calibrates out the Internal Offset Error only. 0 1 1 This calibrates out the Internal Gain Error only. 1 0 0 A Full System Calibration is initiated here where first the Internal DAC is calibrated followed by the System Gain Error, and finally the System Offset Error is calibrated out. 1 0 1 Here the System Gain Error is calibrated out followed by the System Offset Error. 1 1 0 This calibrates out the System Offset Error only. 1 1 1 This calibrates out the System Gain Error only. |
类似零件编号 - AD7856ARS |
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类似说明 - AD7856ARS |
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