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AD7821KP 数据表(PDF) 7 Page - Analog Devices |
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AD7821KP 数据表(HTML) 7 Page - Analog Devices |
7 / 12 page AD7821 REV. A –7– Figure 4. Power Supply as Reference. Unipolar Operation (0 to + 5 V) Figure 5. External Reference. Bipolar Operation (–2.5 V to +2.5 V) INPUT CURRENT The analog input of the AD7821 behaves somewhat differently to conventional A/D converters. This is due to the ADC’s sampled data comparators, which take varying amounts of input current depending on the cycle of the converter. The equivalent input circuit of the AD7821 is shown in Figure 6. When a conversion ends (e.g., falling edge of INT, WR-RD mode, tRD > tINTL) all the input switches are closed and VIN is connected to the comparators of the internal LS and MS ADCs. Therefore, VIN is connected to 31 one-pF input capacitors simultaneously . Figure 6. AD7821 Equivalent Input Circuit The input capacitors must charge to the input voltage through the on resistance of the analog switches (about 2 k Ω to 5 kΩ). In addition, about 12 pF of input stray capacitance must be charged. The analog input can be modeled as an equivalent RC network as shown in Figure 7. As RS (source impedance) increases, the input capacitance takes longer to charge. The comparators track the analog input between conversions. A minimum delay time (tP) of 350 ns is required between conver- sions to allow for voltage source settling and comparator track- ing time. This allows input time constants of 50 ns without settling time problems. Typical total input capacitance values of 55 pF allow RS to be 0.9 k Ω without lengthening t P to give VIN more time to settle. Figure 7. RC Network Model INPUT TRANSIENTS Transients on the analog input signal caused by charging current flowing into VIN will not normally degrade the ADC’s performance. In effect, the AD7821 does not “look” at the in- put when these transients occur. The comparators’ inputs track VIN and are not sampled until the falling edge of WR (WR-RD Mode) or RD (RD Mode), so at least 350 ns (tP) is provided to charge the ADC’s input capacitance. It is, therefore, not neces- sary to filter out these transients with an external capacitor at the VIN terminal. INHERENT TRACK-AND-HOLD A major benefit of the AD7821’s input structure is its ability to measure a variety of high-speed signals without the help of an external track-and-hold. Any ADC which does not have a built- in track-and-hold, regardless of its speed, requires the analog in- put to remain stable to at least 1/2 LSB for the duration of the conversion to maintain full accuracy. This requires the use of a track-and-hold whenever the input is a high-speed signal. The AD7821’s sampled-data comparators, by nature of their input switching, inherently accomplish this track-and-hold function. Although the conversion time for the AD7821 is 660 ns (WR-RD mode, tWR + tRD + tACC1), the time for which VIN must be stable to 1/2 LSB is much smaller. The AD7821 tracks VIN between conversions only, and its value on the falling edge of WR or RD in the WR-RD or RD modes, respectively, is the measured value. SINUSOIDAL INPUTS The bandwidth of the built-in track-and-hold is 100 kHz max (150 kHz typ, 5 V p-p). This is limited by the analog bandwidth of the comparators and timing skew between the comparator switches. This means that the analog input frequency can be up to 100 kHz without the aid of an external track-and-hold. The Nyquist criterion requires that the sampling rate be at least twice the input frequency (i.e., ≥2 100 kHz). This requires an ideal antialiasing filter with an infinite roll-off. To ease the prob- |
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类似说明 - AD7821KP |
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