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AD589SH 数据表(PDF) 2 Page - Analog Devices |
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AD589SH 数据表(HTML) 2 Page - Analog Devices |
2 / 12 page REV. B –2– AD7575–SPECIFICATIONS (VDD = +5 V, VREF = +1.23 V, AGND = DGND = 0 V; fCLK = 4 MHz external; all specifications TMIN to TMAX unless otherwise noted) Parameter J, A Versions 1 K, B Versions S Version T Version Units Conditions/Comments ACCURACY Resolution 8 8 8 8 Bits Total Unadjusted Error ±2 ±1 ±2 ±1 LSB max Relative Accuracy ±1 ±1/2 ±1 ±1/2 LSB max Minimum Resolution for Which No Missing Codes Is Guaranteed 8 8 8 8 Bits max Full-Scale Error +25 °C ±1 ±1 ±1 ±1 LSB max Full-Scale TC Is Typically 5 ppm/ °C TMIN to TMAX ±1 ±1 ±1 ±1 LSB max Offset Error 2 +25 °C ±1/2 ±1/2 ±1/2 ±1/2 LSB max Offset TC Is Typically 5 ppm/ °C TMIN to TMAX ±1/2 ±1/2 ±1/2 ±1/2 LSB max ANALOG INPUT Voltage Range 0 to 2 VREF 0 to 2 VREF 0 to 2 VREF 0 to 2 VREF Volts 1 LSB = 2 VREF/256; See Figure 16 DC Input Impedance 10 10 10 10 M Ω min Slew Rate, Tracking 0.386 0.386 0.386 0.386 V/ µs max SNR 3 45 45 45 45 dB min VIN = 2.46 V p-p @ 10 kHz; See Figure 11 REFERENCE INPUT VREF (For Specified Performance) 1.23 1.23 1.23 1.23 Volts ±5% IREF 500 500 500 500 µA max LOGIC INPUTS CS, RD VINL, Input Low Voltage 0.8 0.8 0.8 0.8 V max VINH, Input High Voltage 2.4 2.4 2.4 2.4 V min IIN, Input Current +25 °C ±1 ±1 ±1 ±1 µA max VIN = 0 or VDD TMIN to TMAX ±10 ±10 ±10 ±10 µA max VIN = 0 or VDD CIN, Input Capacitance 3 10 10 10 10 pF max CLK VlNL, Input Low Voltage 0.8 0.8 0.8 0.8 V max VINH, Input High Voltage 2.4 2.4 2.4 2.4 V min IINL, Input Low Current 700 700 800 800 µA max VINL = 0 V IINH, Input High Current 700 700 800 800 µA max VINH = VDD LOGIC OUTPUTS BUSY, DB0 to DB7 VOL, Output Low Voltage 0.4 0.4 0.4 0.4 V max ISINK = 1.6 mA VOH, Output High Voltage 4.0 4.0 4.0 4.0 V min ISOURCE = 40 µA DB0 to DB7 Floating State Leakage Current ±1 ±1 ±10 ±10 µA max VOUT = 0 to VDD Floating State Output Capacitance 3 10 10 10 10 pF max CONVERSION TIME 4 With External Clock 5 5 5 5 µsf CLK = 4 MHz With Internal Clock, TA = +25°C5 5 5 5 µs min Using Recommended Clock 15 15 15 15 µs max Components Shown in Figure 15 POWER REQUIREMENTS 5 VDD +5 +5 +5 +5 Volts ±5% for Specified Performance IDD 6 6 7 7 mA max Typically 3 mA with VDD = +5 V Power Dissipation 15 15 15 15 mW typ Power Supply Rejection ±1/4 ±1/4 ±1/4 ±1/4 LSB max 4.75 V ≤ V DD ≤ 5.25 V NOTES 1Temperature ranges are as follows: J, K Versions; 0 °C to +70°C A, B Versions; –25 °C to +85°C S, T Versions; –55 °C to +125°C 2Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB. 3Sample tested at +25 °C to ensure compliance. 4Accuracy may degrade at conversion times other than those specified. 5Power supply current is measured when AD7575 is inactive i.e., when CS = RD = BUSY = logic HIGH. Specifications subject to change without notice. |
类似零件编号 - AD589SH |
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类似说明 - AD589SH |
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