AD74322DAR datasheet(11/20 Pages) AD

部件名	AD74322DAR

功能描述	Low Cost, Low Power Stereo Audio Analog Front End

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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AD74322

–11–

Pr D

03/00

PRELIMINARY TECHNICAL DATA

PRELIMINAR

Y

TECHNICAL

DA

TA

INTERFACING

TheAD74322featurestwoseparateinterfaces,ControlandData,which

areusedtoprogramcontrolsettingsandsend/receivesampledata

respectively.TheControlinterfaceisimplementedusinganSPI

type

protocolbuttransfers16-bitsperframe.TheDatainterfaceuseseithera

DSPor I

2S

protocoltotransferstereodatasamplesbetweencontroller

andcodec.TheDSPcompatibleinterfacemodeallowsdatasamplestobe

transferredinaprotocolthatissupportedbytheserialinterfacesofmost

fixed-andfloating-pointDSPs.

InordertoreduceperipheralrequirementswheninterfacingtheAD74322

withthehostDSP,theDSPmodeallowstheDSPtosendbothdataand

controlinformationtothedeviceviathedatainterface.Thisisthedefault

modeandrequiresuserstoonlyuseasingleDSPSPORTtobothcontrol

thedeviceandserviceitwithdatasamples.

ControlInterface

ControloftheAD74322operationisviaasetof16ControlRegisters

whichareprogrammedthroughtheControlPort.TheControlPort

protocolissimilartotheSPIÒprotocolwiththeexceptionthat16-bitsof

dataaretransferredperframe.TheControlPortconsistsofthefollowing

pins:CCLK-ControlPortSerialClock,CLATCH-ControlPortLatch

orFramesignal,CDIN-ControlPortSerialDataInandCDOUT-

ControlPortDataOut.CLATCHisaframingsignalthatisactivelow.

Whenasserted,itgatestheotherinterfacelinesasbeingactive.CCLKis

usedtoclockinputdataonCDINandclockoutput(readback)dataon

CDOUT.Figure<Control_Interface>detailstheconnectivityofthe

ControlPorttoacontrollerandFigure<Control_Timing>detailsthe

interfacetiming.

CDIN

CLATCH

CCLK

CDOUT

AD743xx

CONTROLLER

Figure <Control_Interface>

CLATCH

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

CCLK

CDIN

CDOUT

MSB

14

13

12

11

10

9

8

7

6

5

4

3

2

1

LSB

Figure <Control_Timing>

Data in and out of the Control Port go through a 16-bit

shift register whose contents are mapped to the internal

registers using the mapping scheme of Figure

<ContPortMap>. A 16-bit word received by the Control

Port is decoded as a read or write to a register address set

by bits 15 - 12. This 4-bit register address selects 1 of 16

registers as shown in Table <ContRegMap>. Bit 11

selects whether a register read or write is requested -

Write = 0, Read = 1. Bit-10 is reserved. Bits 9 through 0

contain register data. Each Control register’s contents are

detailed below.

DataInterface

Therearetwomodesofoperationofthedatainterface:DSPmodeand

I2Smode.ThedefaultmodeofthedatainterfaceisaDSPmodewhich

combinescontrolanddatafunctionsinasingleprotocol.Thisistoreduce

theperipheraloverheadrequiredontheDSPwheninterfacingtothe

AD74322.ThismodeoperatesinastandardDSPserialformat.InI2S

modethedatainterfacestreamsaudiodatasamplesbeingsenttoor

receivedfromtheDACsandADCsrespectively,usingtheI2Sserial

protocol.

Ineithermodeitcanbeconfiguredaseitheramasterorslavedevice

ensuringconnectivitytothelargestnumberofhostprocessors.

DSPMode

TheDSPmodeallowsinterfacingtomostfixed-andfloating-pointDSPs

aswellasotherprocessorssuchasRISCsetcthathavingserialportsthat

supportsynchronouscommunications.Thekeyfeatureofsynchronous

DSPcommunicationsisthattheserialdataisframedbyaseparateFrame

Syncsignal.Figures<Data_DSP_Slave>and<Data_DSP_Master>detail

connectivityinMasterMode(codecismaster)andSlaveMode(codecis

slave)respectively.

LRCLK/SDIFS

SDOFS

DSDATA/SDI

BCLK/SCLK

ASDATA/SDO

AD743xx

(MASTER)

TFS

DT

SCLK

DR

RFS

DSP

(SLAVE)

Figure <Data_DSP_Slave>

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类似说明 - AD74322DAR

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