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AD7305 数据表(PDF) 5 Page - Analog Devices |
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AD7305 数据表(HTML) 5 Page - Analog Devices |
5 / 14 page –5– AD7304/AD7305 REV. A Table III. AD7305 Control Logic Truth Table WR A1 A0 LDAC Input Register Function DAC Register Function LLLH REG A Loaded with DB0–DB7 Latched with Previous Contents, No Change ↑+ L L H REG A Latched with DB0–DB7 Latched with Previous Contents, No Change L L H H REG B Loaded with DB0–DB7 Latched with Previous Contents, No Change ↑+ L H H REG B Latched with DB0–DB7 Latched with Previous Contents, No Change L H L H REG C Loaded with DB0–DB7 Latched with Previous Contents, No Change ↑+ H L H REG C Latched with DB0–DB7 Latched with Previous Contents, No Change L H H H REG D Loaded with DB0–DB7 Latched with Previous Contents, No Change ↑+ H H H REG D Latched with DB0–DB7 Latched with Previous Contents, No Change H X X L No Effect All Input Register Contents Loaded, Register Transparent L X X L Input REG x Transparent to DB0–DB7 Register Transparent HX X ↑+ No Effect All Input Register Contents Latched H X X H No Effect, Device Not Selected No Effect, Device Not Selected NOTES 1 ↑+ positive logic transition; ↓– negative logic transition; X Don’t Care. 2 LDAC is a level sensitive input. PIN CONFIGURATIONS TOP VIEW (Not to Scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VOUTB VOUTA VSS VREFB VREFA GND LDAC CLR VOUTC VOUTD VDD VREFC VREFD SDI/SHDN CLK CS AD7304 TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 AD7305 DB5 DB6 VOUTA VSS VREF DB7 LDAC GND DB2 DB1 VOUTD VDD A0/SHDN DB0 WR A1 VOUTB VOUTC DB4 DB3 tAH tDH tLH tLDW tWR tAS tDS tLS tS 1 LSB ERROR BAND A0, A1 WR D0–D7 LDAC VOUT Figure 4. AD7305 Timing Diagram tSDR A0/SHDN IDD tSDN Figure 5. AD7305 Timing Diagram |
类似零件编号 - AD7305 |
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类似说明 - AD7305 |
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