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AD7303BN 数据表(PDF) 10 Page - Analog Devices |
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AD7303BN 数据表(HTML) 10 Page - Analog Devices |
10 / 16 page AD7303 –10– REV. 0 Bit Location Mnemonic Description DB15 INT /EXT Selects between internal and external reference. DB14 X Uncommitted bit. DB13 LDAC Load DAC bit for synchronous update of DAC outputs. DB12 PDB Power-down DAC B. DB11 PDA Power-down DAC A. DB10 A /B Address bit to select either DAC A or DAC B. DB9 CR1 Control Bit 1 used in conjunction with CR0 to implement the various data loading functions. DB8 CR0 Control Bit 0 used in conjunction with CR1 to implement the various data loading functions. DB7–DB0 Data These bits contain the data used to update the output of the DACs. DB7 is the MSB and DB0 the LSB of the 8-bit data word. CONTROL BITS LDAC A /B CR1 CR0 Function Implemented 0 X 0 0 Both DAC registers loaded from shift register. 0 0 0 1 Update DAC A input register from shift register. 0 1 0 1 Update DAC B input register from shift register. 0 0 1 0 Update DAC A DAC register from input register. 0 1 1 0 Update DAC B DAC register from input register. 0 0 1 1 Update DAC A DAC register from shift register. 0 1 1 1 Update DAC B DAC register from shift register. 1 0 X X Load DAC A input register from shift register and update both DAC A and DAC B DAC registers. 1 1 X X Load DAC B input register from shift register and update both DAC A and DAC B DAC registers outputs. INT /EXT Function 0 Internal VDD/2 reference selected. 1 External reference selected; this external reference is applied at the REF pin and ranges from 1 V to VDD/2. PDA PDB Function 0 0 Both DACs active. 0 1 DAC A active and DAC B in power-down mode. 1 0 DAC A in power-down mode and DAC B active. 1 1 Both DACs powered down. DB15 (MSB) DB0 (LSB) INT /EXT X LDAC PDB PBA A /B CR1 CR0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 |––––––––––––––––––––––––– Control Bits –––––––––––––––––––––––––|––––––––––––––––––––––––– Data Bits –––––––––––––––––––––––––| Figure 24. Input Shift Register Contents |
类似零件编号 - AD7303BN |
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类似说明 - AD7303BN |
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