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AD712AH 数据表(PDF) 9 Page - Analog Devices

部件名 AD712AH
功能描述  Dual Precision, Low Cost, High Speed, BiFET Op Amp
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD712AH 数据表(HTML) 9 Page - Analog Devices

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AD712
REV. B
–9–
The photos of Figures 28a and 28b show the dynamic response
of the AD712 in the settling test circuit of Figure 29.
100
10
0%
500ns
90
5mV
5V
Figure 28a. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
100
10
0%
500ns
90
5mV
5V
Figure 28b. Settling Characteristics 0 V to –10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2 and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 10, amplifying the error
signal output of A1.
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique
such as that shown in Figure 30, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should not
be extended for any unnecessary length on the printed circuit
board.
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
TO-99 (H) PACKAGE
PLASTIC MINI-DIP (N) PACKAGE
CERDIP (Q) PACKAGE
AND SOIC (R) PACKAGE
Figure 30. Board Layout for Guarding Inputs
+15V
0.1 F
1/2
AD712
10pF
–15V
5k
4.99k
0.47 F
1/2
AD712
0.47 F
200
4.99k
5-18pF
0.1 F
10k
10k
VIN
VERROR
5
HP2835
HP2835
20pF
1M
10k
0.2-0.6pF
1.1k
5pF
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
DATA
DYNAMICS
5109
(OR EQUIVALENT
FLAT TOP
PULSE
GENERATION)
205
–15V +15V
VOUT
Figure 29. Settling Time Test Circuit


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