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AD698AP 数据表(PDF) 8 Page - Analog Devices |
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AD698AP 数据表(HTML) 8 Page - Analog Devices |
8 / 12 page REV. B –8– AD698 Note that VOS should be chosen so that R3 cannot have negative value . Figure 12 shows the desired response. +5 +0.1d (INCHES) –0.1 V OUT (VOLTS) +10 Figure 12. VOUT (0 V–10 V Full Scale) vs. Displacement ( ±0.1 Inch) DESIGN PROCEDURE SINGLE SUPPLY OPERATION Figure 13 shows the single supply connection method. R1 C1 C2 C3 R4 R3 13 16 15 14 24 23 22 21 20 19 18 17 12 11 10 9 8 1 2 3 4 7 6 5 AD698 –VS EXC1 EXC2 LEV1 LEV2 FREQ1 BFILT1 BFILT2 –BIN +BIN –AIN FREQ2 SIG REF OFFSET2 OFFSET1 +VS OUT FILT FEEDBACK SIG OUT –ACOMP AFILT2 AFILT1 +ACOMP +AIN C4 R2 1000pF SIGNAL REFERENCE RL VOUT 0.1µF Vps +30V 6.8µF 1M R6 R5 C5 AB C D PHASE LAG/LEAD NETWORK RT AB CD PHASE LEAD RS C C RS RS RT A B CD PHASE LAG C PHASE LAG = Arc Tan (Hz RC); PHASE LEAD = Arc Tan 1/(Hz RC) WHERE R = RS// (RS + RT) Figure 13. Interconnection Diagram for Single Supply Operation For single supply operation, repeat Steps 1 through 10 of the design procedure for dual supply operation. R5, R6 and C5 are additional component values to be determined. VOUT is mea- sured with respect to SIGNAL REFERENCE. 10. Compute a maximum value of R5 and R6 based upon the relationship R5 + R6 ≤ V PS/100 µA 11. The voltage drop across R5 must be greater than 2 + 10 kΩ 1.2V R4 + 2 kΩ + 250 µA + VOUT 4 × R2 Volts Therefore R5 ≥ 2 + 10 kΩ 1.2V R4 + 2 kΩ + 250 µA + VOUT 4 × R2 100 µA Ohms Based upon the constraints of R5 + R6 (Step 10) and R5 (Step 11), select an interim value of R6. 12. Load current through RL returns to the junction of R5 and R6, and flows back to VPS. Under maximum load condi- tions, make sure the voltage drop across R5 is met as de- fined in Step 11. As a final check on the power supply voltages, verify that the peak values of VA and VB are at least 2.5 volts less than the voltage between +VS and –VS. 13. C5 is a bypass capacitor in the range of 0.1 µF to 1 µF. Gain Phase Characteristics To use an LVDT in a closed-loop mechanical servo application, it is necessary to know the dynamic characteristics of the trans- ducer and interface elements. The transducer itself is very quick to respond once the core is moved. The dynamics arise prima- rily from the interface electronics. Figures 14, 15 and 16 show the frequency response of the AD698 LVDT Signal Conditioner. Note that Figures 15 and 16 are basically the same; the differ- ence is frequency range covered. Figure 15 shows a wider range of mechanical input frequencies at the expense of accuracy. FREQUENCY – Hz 0 10k 100 1k 10 0 –30 –60 –70 0 –10 –20 –50 –40 –360 –60 –240 –300 –420 –180 –120 0.1µF 0.33µF 2.0µF R2 = 81k Ω fEXC = 2.5kHz 0.1µF 0.33µF 2.0µF R2 = 81k Ω fEXC = 2.5kHz Figure 14. Gain and Phase Characteristics vs. Frequency (0 kHz–10 kHz) |
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类似说明 - AD698AP |
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