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AD677 数据表(PDF) 9 Page - Analog Devices |
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AD677 数据表(HTML) 9 Page - Analog Devices |
9 / 16 page AD677 REV. A –9– in Figure 3. In this circuit BUSY is used to reset the circuitry which divides the system clock down to provide the AD677 CLK. This serves to interrupt the clock until after the input sig- nal has been acquired, which has occurred when BUSY goes HIGH. When the conversion is completed and BUSY goes LOW, the circuit in Figure 3 truncates the 17th CLK pulse width which is tolerable because only its rising edge is critical. 5 2 1 7 12 9 4 11 12.288MHz SYSTEM CLOCK CLK 74HC175 2D 1Q CLR 3D 2Q 3Q 1D BUSY CLK AD677 SAMPLE 2 8 9 12 6 13 1 1QD 74HC393 1CLR 2CLR 2QD 2QC 1CLK 2CLK Figure 3. Figure 3 also illustrates the use of a counter (74HC393) to de- rive the AD677 SAMPLE command from the system clock when a continuous convert mode is desirable. Pin 9 (2QC) pro- vides a 96 kHz sample rate for the AD677 when used with a 12.288 MHz system clock. Alternately, Pin 8 (2QD) could be used for a 48 kHz rate. If a continuous clock is used, then the user must avoid CLK edges at the instant of disconnecting VIN which occurs at the falling edge of SAMPLE (see tFCD specification). The duty cycle of CLK may vary, but both the HIGH (tCH) and LOW (tCL) phases must conform to those shown in the timing specifica- tions. The internal comparator makes its decisions on the rising edge of CLK. To avoid a negative edge transition disturbing the comparator’s settling, tCL should be at least half the value of tCLK. It is not recommended that the SAMPLE pin change state toward the end of a CLK cycle, in order to avoid transitions dis- turbing the internal comparator’s settling. During a conversion, internal dc error terms such as comparator voltage offset are sampled, stored on internal capacitors and used to correct for their corresponding errors when needed. Be- cause these voltages are stored on capacitors, they are subject to leakage decay and so require refreshing. For this reason there is a maximum conversion time tC (1000 µs). From the time SAMPLE goes HIGH to the completion of the 17th CLK pulse, no more than 1000 µs should elapse for specified performance. However, there is no restriction to the maximum time between individual conversions. Output coding for the AD677 is twos complement as shown in Table I. The AD677 is designed to limit output coding in the event of out-of-range input. Table I. Serial Output Coding Format (Twos Complement) VIN Output Code <Full Scale 011 . . . 11 Full Scale 011 . . . 11 Full Scale – 1 LSB 011 . . . 10 Midscale + 1 LSB 000 . . . 01 Midscale 000 . . . 00 Midscle – 1 LSB 111 . . . 11 –Full Scale + 1 LSB 100 . . . 01 –Full Scale 100 . . . 00 <–Full Scale 100 . . . 00 POWER SUPPLIES AND DECOUPLING The AD677 has three power supply input pins. VCC and VEE provide the supply voltages to operate the analog portions of the AD677 including the capacitor DAC, input buffers and com- parator. VDD provides the supply voltage which operates the digital portions of the AD677 including the data output buffers and the autocalibration controller. As with most high performance linear circuits, changes in the power supplies can produce undesired changes in the perfor- mance of the circuit. Optimally, well regulated power supplies with less than 1% ripple should be selected. The ac output im- pedance of a power supply is a complex function of frequency, and in general will increase with frequency. In other words, high frequency switching such as that encountered with digital cir- cuitry requires fast transient currents which most power supplies cannot adequately provide. This results in voltage spikes on the supplies. If these spikes exceed the ±5% tolerance of the ±12 V supplies or the ±10% limits of the +5 V supply, ADC perfor- mance will degrade. Additionally, spikes at frequencies higher than 100 kHz will also degrade performance. To compensate for the finite ac output impedance of the supplies, it is necessary to store “reserves” of charge in bypass capacitors. These capacitors can effectively lower the ac impedance presented to the AD677 power inputs which in turn will significantly reduce the magni- tude of the voltage spikes. For bypassing to be effective, certain guidelines should be followed. Decoupling capacitors, typically 0.1 µF, should be placed as closely as possible to each power supply pin of the AD677. It is essential that these capacitors be placed physically close to the IC to minimize the inductance of the PCB trace between the capacitor and the supply pin. The logic supply (VDD) should be decoupled to digital common and the analog supplies (VCC and VEE) to analog common. The ref- erence input is also considered as a power supply pin in this re- gard and the same decoupling procedures apply. These points are displayed in Figure 4. +5V +12V –12V SYSTEM ANALOG COMMON SYSTEM DIGITAL COMMON AGND DGND AD677 VEE VCC VREF VDD 0.1µF 0.1µF 0.1µF 0.1µF Figure 4. Grounding and Decoupling the AD677 |
类似零件编号 - AD677 |
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类似说明 - AD677 |
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