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AD6622S 数据表(PDF) 3 Page - Analog Devices

部件名 AD6622S
功能描述  Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
Download  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD6622S 数据表(HTML) 3 Page - Analog Devices

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AD6622
–3–
REV. 0
TIMING CHARACTERISTICS1
Test
AD6622AS
Name
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
CLK Timing Requirements:
tCLK
CLK Period
Full
IV
13.3
ns
tCLKL
CLK Width Low
Full
IV
5.5
0.5
× t
CLK
ns
tCLKH
CLK Width High
Full
IV
5.5
0.5
× tCLK
ns
RESET Timing Requirements:
tRESL
RESET Width Low
Full
IV
30.0
ns
Input Wideband Data Timing Requirements:
tSI
Input to CLK Setup Time
Full
IV
0.5
ns
tHI
Input to CLK Hold Time
Full
IV
3.5
ns
Parallel Output Switching Characteristics:
tSO
CLK to Output Setup Time
Full
IV
12
ns
tHO
CLK to Output Hold Time
Full
IV
4.1
ns
tZO
Output Three-State Time
Full
V
5
ns
SYNC Timing Requirements:
tSS
SYNC to CLK Setup Time
Full
IV
2.6
ns
tHS
SYNC to CLK Hold Time
Full
IV
1.5
ns
Serial Port Timing Requirements:
tDSCLK
CLK to SCLK Delay
Full
V
8.5
ns
tDSDFS
SCLK to SDFS Delay
Full
IV
–1.2
+2.4
ns
tSSI
SDI to SCLK Setup Time
Full
IV
8.5
ns
tHSI
SDI to SCLK Hold Time
Full
IV
5.5
ns
tSCS
Serial Clock Skew
Full
IV
7
ns
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM Write Timing:
tHWR
WR(R/W) to RDY(DTACK) Hold Time
Full
IV
0
ns
tSAM
Address/Data to
WR(R/W) Setup Time
Full
IV
0
ns
tHAM
Address/Data to RDY(
DTACK) Hold Time
Full
IV
0
ns
tDRDY
WR(R/W) to RDY(DTACK) Delay
Full
IV
10.2
ns
tACCFAST
WR(R/W) to RDY(DTACK) High Delay
Full
IV
2
× tCLK
3
× tCLK
ns
tACCMEDIUM
WR(R/W) to RDY(DTACK) High Delay
Full
IV
3
× t
CLK
4
× t
CLK
ns
tACCSLOW
WR(R/W) to RDY(DTACK) High Delay
Full
IV
4
× tCLK
5
× tCLK
ns
MODE INM Read Timing:
tSAM
Address to
RD(DS) Setup Time
Full
IV
0
ns
tHA
Address to Data Hold Time
Full
IV
0
ns
tZD
Data Three-State Delay
Full
IV
3.4
7
10.5
ns
tDD
RDY(
DTACK) to Data Delay
Full
IV
tCLK – 10
ns
tDRDY
RD(DS) to RDY(DTACK) Delay
Full
IV
10.2
ns
tACCFAST
RD(DS) to RDY(DTACK) High Delay
Full
IV
2
× t
CLK
3
× t
CLK
ns
tACCMEDIUM
RD(DS) to RDY(DTACK) High Delay
Full
IV
3
× tCLK
4
× tCLK
ns
tACCSLOW
RD(DS) to RDY(DTACK) High Delay
Full
IV
4
× tCLK
5
× tCLK
ns
(CLOAD = 40 pF, all outputs unless specified)


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