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AD606JR-REEL7 数据表(PDF) 5 Page - Analog Devices |
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AD606JR-REEL7 数据表(HTML) 5 Page - Analog Devices |
5 / 12 page AD606 REV. B –5– ILOG and OPCM (output common, which is usually grounded). The nominal slope at this point is 18.75 mV/dB (375 mV/ decade). In applications where VLOG is taken to an A/D converter which allows the use of an external reference, this reference input should also be connected to the same +5 V supply. The power supply voltage may be in the range +4.5 V to +5.5 V, providing a range of slopes from nominally 33.75 mV/dB (675 mV/ de- cade) to 41.25 mV/dB (825 mV/decade). A buffer amplifier, having a gain of two, provides a final output scaling at VLOG of 37.5 mV/dB (750 mV/decade). This low- impedance output can run from close to ground to over +4 V (using the recommended +5 V supply) and is tolerant of resis- tive and capacitive loads. Further filtering is provided by a con- jugate pole pair, formed by internal capacitors which are an integral part of the output buffer. The corner frequency of the overall filter is 2 MHz, and the 10%–90% rise time is 150 ns. Later, we will show how the slope and intercept can be altered using simple external adjustments. The direct buffer input BFIN is used in these cases. The last limiter output is available as complementary currents from open collectors at pins LMHI and LMLO. These currents are each 1.2 mA typical with LADJ grounded and may be con- verted to voltages using external load resistors connected to VPOS; typically, a 200 Ω resistor is used on just one output. The voltage gain is then over 90 dB, resulting in a hard-limited output for all input levels down to the noise floor. The phasing is such that the voltage at LMHI goes high when the input (INHI to INLO) is positive. The overall delay time from the signal inputs to the limiter outputs is 8 ns. Of particular impor- tance is the phase stability of these outputs versus input level. At 50 MHz, the phase typically remains within ±4° from –70 dBm to +5 dBm. The rise time of this output (essentially a square wave) is about 1.2 ns, resulting in clean operation to more than 70 MHz. for that converter should be a fractional part of VPOS, if possible. The slope is essentially independent of temperature. The intercept PX is essentially independent of either the supply voltage or temperature. However, the AD606 is not factory calibrated, and both the slope and intercept may need to be externally adjusted. Following calibration, the conformance to an ideal logarithmic law will be found to be very close, particu- larly at moderate frequencies (see Figure 14), and still accept- able at the upper end of the frequency range (Figure 15). CIRCUIT DESCRIPTION Figure 2 is a block diagram of the AD606, which is a complete logarithmic amplifier system in monolithic form. It uses a total of nine limiting amplifiers in a “successive detection” scheme to closely approximate a logarithmic response over a total dynamic range of 90 dB (Figure 2). The signal input is differential, at nodes INHI and INLO, and will usually be sinusoidal and ac coupled. The source may be either differential or single-sided; the input impedance is about 2.5 k Ω in parallel with 2 pF. Seven of the amplifier/detector stages handle inputs from –80 dBm (32 µV rms) up to about –14 dBm (45 mV rms). The noise floor is about –83 dBm (18 µV rms). Another two stages receive the input attenuated by 22.3 dB, and respond to inputs up to +10 dBm (707 mV rms). The gain of each of these stages is 11.15 dB and is accurately stabilized over temperature by a precise biasing system. The detectors provide full-wave rectification of the alternating signal present at each limiter output. Their outputs are in the form of currents, proportional to the supply voltage. Each cell incorporates a low-pass filter pole, as the first step in recovering the average value of the demodulated signal, which contains appreciable energy at even harmonics of the input frequency. A further real pole can be introduced by adding a capacitor be- tween the summing node ISUM and VPOS. The summed de- tector output currents are applied to a 6:1 reduction current mirror. Its output at ILOG is scaled 2 µA/dB, and is converted to voltage by an internal load resistor of 9.375 k Ω between REFERENCE AND POWER-UP ONE-POLE FILTER FINAL LIMITER MAIN SIGNAL PATH 11.15dB/STAGE OFFSET-NULL LOW-PASS FILTER 30pF 30pF 360k 360k 2pF 9.375k 9.375k 2pF X2 TWO-POLE SALLEN-KEY FILTER 12 A/dB 2 A/dB HIGH-END DETECTORS AD606 1.5k 1.5k 250 30k 30k 9 10 11 12 13 14 15 16 12 345 67 8 INLO COMM ISUM ILOG BFIN VLOG OPCM LMLO LMHI LADJ FIL2 FIL1 VPOS PRUP COMM INHI X1 Figure 2. Simplified Block Diagram |
类似零件编号 - AD606JR-REEL7 |
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类似说明 - AD606JR-REEL7 |
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