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AD5315 数据表(PDF) 3 Page - Analog Devices |
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AD5315 数据表(HTML) 3 Page - Analog Devices |
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3 / 20 page  REV. 0 –3– AD5334/AD5335/AD5336/AD5344 AC CHARACTERISTICS 1 B Version3 Parameter 2 Min Typ Max Unit Conditions/Comments Output Voltage Settling Time VREF = 2 V. See Figure 20 AD5334 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H) AD5335 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5336 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5344 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) Slew Rate 0.7 V/ µs Major Code Transition Glitch Energy 8 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.5 nV-s Digital Crosstalk 3 nV-s Analog Crosstalk 0.5 nV-s DAC-to-DAC Crosstalk 3.5 nV-s Multiplying Bandwidth 200 kHz VREF = 2 V ± 0.1 V p-p. Unbuffered Mode Total Harmonic Distortion –70 dB VREF = 2.5 V ± 0.1 V p-p. Frequency = 10 kHz NOTES 1Guaranteed by design and characterization, not production tested. 2See Terminology section. 3Temperature range: B Version: –40 °C to +105°C; typical specifications are at 25°C. Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2, 3 Parameter Limit at TMIN, TMAX Unit Condition/Comments t1 0 ns min CS to WR Setup Time t2 0 ns min CS to WR Hold Time t3 20 ns min WR Pulsewidth t4 5 ns min Data, GAIN, HBEN Setup Time t5 4.5 ns min Data, GAIN, HBEN Hold Time t6 5 ns min Synchronous Mode. WR Falling to LDAC Falling. t7 5 ns min Synchronous Mode. LDAC Falling to WR Rising. t8 4.5 ns min Synchronous Mode. WR Rising to LDAC Rising. t9 5 ns min Asynchronous Mode. LDAC Rising to WR Rising. t10 4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling. t11 20 ns min LDAC Pulsewidth t12 20 ns min CLR Pulsewidth t13 50 ns min Time Between WR Cycles t14 20 ns min A0, A1 Setup Time t15 0 ns min A0, A1 Hold Time NOTES 1Guaranteed by design and characterization, not production tested. 2All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (VIL + VIH)/2. 3See Figure 1. Specifications subject to change without notice. (VDD = 2.5 V to 5.5 V. RL = 2 k to GND; CL = 200 pF to GND. All specifications TMIN to TMAX unless other- wise noted.) t15 t14 t8 CS WR DATA, GAIN, HBEN LDAC1 LDAC2 CLR NOTES: 1 SYNCHRONOUS LDAC UPDATE MODE 2 ASYNCHRONOUS LDAC UPDATE MODE A0, A1 t1 t2 t5 t3 t13 t4 t7 t6 t9 t10 t11 t12 Figure 1. Parallel Interface Timing Diagram (VDD = 2.5 V to 5.5 V, All specifications TMIN to TMAX unless otherwise noted.) |
类似零件编号 - AD5315 |
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类似说明 - AD5315 |
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