AD5551/AD5552

–3–

REV. 0

SCLK

CS

DIN

DB13

DB0

Figure 1. Timing Diagram

Parameter

All Versions

Unit

Description

25

MHz max

SCLK Cycle Frequency

40

ns min

SCLK Cycle Time

20

ns min

SCLK High Time

20

ns min

SCLK Low Time

15

ns min

CS Low to SCLK High Setup

15

ns min

CS High to SCLK High Setup

35

ns min

SCLK High to

CS Low Hold Time

20

ns min

SCLK High to

CS High Hold Time

15

ns min

Data Setup Time

0

ns min

Data Hold Time

30

ns min

LDAC Pulsewidth

30

ns min

CS High to LDAC Low Setup

30

ns min

CS High Time Between Active Periods

NOTES

90% of +3 V and timed from a voltage level of +1.6 V).

Specifications subject to change without notice.

otherwise noted.)