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AD5532HS 数据表(PDF) 9 Page - Analog Devices |
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AD5532HS 数据表(HTML) 9 Page - Analog Devices |
9 / 12 page REV. 0 AD5532HS –9– MICROPROCESSOR INTERFACING AD5532HS-to-ADSP-21xx Interface The ADSP-21xx family of DSPs are easily interfaced to the AD5532HS without the need for extra logic. A data transfer is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5532HS on the falling edge of its SCLK. The easiest way to provide the 19-bit data-word required by the AD5532HS, is to transmit two 10-bit data-words from the ADSP-21xx. Ensure that the data is positioned correctly in the TX register so that the first 19 bits transmitted contain valid data. The SPORT control register should be set up as follows: TFSW = 1, Alternate Framing INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data ISCLK = 1, Internal Serial Clock TFSR = 1, Frame Every Word ITFS = 1, Internal Framing Signal SLEN = 1001, 10-Bit Data Word Figure 3 shows the connection diagram. SCLK AD5532HS* SYNC TFS DIN DT SCLK ADSP-2101/ ADSP-2103* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface AD5532HS-to-MC68HC11 Interface The Serial Peripheral Interface (SPI) on the MC68HC11 is configured for Master Mode (MSTR = 1), Clock Polarity Bit (CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is configured by writing to the SPI Control Register (SPCR)—see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5532HS and the MOSI output drives the serial data line (DIN) of the AD5532HS. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5532HS, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. The 68HC11 transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. See Figure 4. SCLK AD5532HS* SYNC DIN PC7 SCK MC68HC11* *ADDITIONAL PINS OMITTED FOR CLARITY MOSI Figure 4. AD5532HS-to-MC68HC11 Interface AD5532HS-to-PIC16C6x/7x Interface The PIC16C6x/7x Synchronous Serial Port (SSP) is configured as an SPI Master with the Clock Polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See user PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5532HS. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive write operations are necessary to transmit 19 bits of data. Data is transmitted MSB first. It is important to left-justify the data in the SPDR register so that the first 19 bits transmitted contain valid data. RA1 must be pulled low to start a transfer. It is taken high and pulled low again before any further write cycles can take place. Figure 5 shows the connection diagram. SCLK PIC16C6x/7x* SYNC DIN SCK/RC3 AD5532HS* *ADDITIONAL PINS OMITTED FOR CLARITY SDI/RC4 RA1 Figure 5. AD5532HS-to-PIC16C6x/7x Interface AD5532HS-to-8051 Interface The AD5532HS requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode serial data exits the 8051 through RxD and a shift clock is output on TxD. The SYNC signal is derived from a port line (P1.1). Figure 6 shows how the 8051 is connected to the AD5532HS. Because the AD5532HS shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. Note also that the AD5532HS requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. AD5532HS* SCLK DIN SYNC TxD RxD P1.1 8051* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 6. AD5532HS-to-8051 Interface |
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