PRELIMINARY TECHNICAL DATA

AD5280/AD5282

REV PrE 12 MAR 02

7

Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final

product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL 408 382-3107; FAX 408 382-2721; email; walt.heinzer@analog.com

Ω, when V

following RDAC latch codes. Result will be the same if terminal

B is tied to W:

D

Output State

(DEC)

(

Ω)

256

60

Full-Scale

128

10060

Mid-Scale

1

19982

1 LSB

0

20060

Zero-Scale

channel-to-channel matches within ±1%. Device to device

matching is process lot dependent and is possible to have ±30%

variation. Since the resistance element is processed in thin film

ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates output voltages at

wiper-to-B and wiper-to-A to be proportional to the input

voltage at A-to-B. Let’s ignore the effect of the wiper resistance

at the moment. For example connecting A–terminal to +5V and

B–terminal to ground produces an output voltage at the wiper-

to-B starting at zero volts up to 1 LSB less than +5V. Each LSB

of voltage is equal to the voltage applied across terminal AB

divided by the 256 position of the potentiometer divider. Since

AD5280/AD5282 can be supplied by dual supplies, the general

ground for any given input voltage applied to terminals AB is:

3

eqn.

256

256

256

)

(

B

A

W

V

D

V

D

D

V

−

+

=

where D is decimal equivalent of the binary code which is

loaded in the 8-bit RDAC register.

Operation of the digital potentiometer in the divider mode

results in a more accurate operation over temperature. Unlike

the rheostat mode, the output voltage is dependent on the ratio

therefore, the temperature drift reduces to 5ppm/°C.

DIGITAL INTERFACE

2-WIRE SERIAL BUS

serial bus. The RDACs are connected to this bus as slave

devices.

Referring from Figures 2 and 3, the first byte of

AD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave

address and a R/

W bit. The 5 MSBs are 01011 and the following

2 bits are determined by the state of the AD0 and AD1 pins of

the device. AD0 and AD1 allow the user to use up to four of

these devices on one bus.

1.

The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the

SDA line occurs while SCL is high, Figure 2. The

following byte is the Slave Address Byte which consists of

the 7-bit slave address followed by an R/

W bit (this bit

determines whether data will be read from or written to the

slave device).

The slave whose address corresponds to the transmitted

address responds by pulling the SDA line low during the

ninth clock pulse (this is termed the Acknowledge bit). At

this stage, all other devices on the bus remain idle while the

selected device waits for data to be written to or read from

its serial register. If the R/

W bit is high, the master will read

from the slave device. On the other hand, if the R/

W bit is

low, the master will write to the slave device.

2.

A Write operation contains an extra Instruction Byte more

than the Read operation. Such Instruction Byte in Write

mode follows the Slave Address Byte. The MSB of the

Instruction Byte labeled

A/B is the RDAC sub-address

select. A “low” select RDAC1 and a “high” selects RDAC2

for dual channel AD5282. The 2

scale reset. A logic high of this bit moves the wiper of a

rd

MSB SD is a shutdown bit. A logic high causes the RDAC

open circuit at terminal A while shorting wiper to terminal

B. This operation yields almost a zero Ohm in rheostat

mode or zero volt in potentiometer mode. This SD bit

serves the same function as the

SHDN pin except it reacts in

active low. The following two bits are O2 and O1. They are

extra programmable logic output that users can make use of

them by driving other digital loads, logic gates, LED

drivers, and analog switches, etc. The 3 LSBs are DON’T

CARE. See Figure 2.

3.

After acknowledged the Instruction Byte, the last byte in

Write mode is the Data Byte. Data is transmitted over the

serial bus in sequences of nine clock pulses (eight data bits

followed by an “Acknowledge” bit). The transitions on the

SDA line must occur during the low period of SCL and

remain stable during the high period of SCL, Figure 1.

4.

In Read mode, the Data Byte goes right after the

acknowledgment of the Slave Address Byte. Data is

transmitted over the serial bus in sequences of nine clock

pulses (slight difference with the Write mode, there are

eight data bits followed by a “No Acknowledge” bit).

Similarly, the transitions on the SDA line must occur

during the low period of SCL and remain stable during the

high period of SCL.

5.

When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is

defined as a low-to-high transition on the SDA line while

SCL is high. In Write mode, the master will pull the SDA

line high during the 10