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AD5204BRU10 数据表(PDF) 10 Page - Analog Devices |
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AD5204BRU10 数据表(HTML) 10 Page - Analog Devices |
10 / 11 page AD5204/AD5206 –10– REV. 0 RDAC 1 RDAC 2 RDAC 4/6 AD5204/AD5206 SDI CLK CS ADDR DECODE SERIAL REGISTER Figure 18. Equivalent Input Control Logic The target RDAC latch is loaded with the last eight bits of the serial data word completing one DAC update. Four separate 8- bit data words must be clocked in to change all four VR settings. SERIAL REGISTER SDI CK RS D Q SHDN CS CLK PR SDO GND Figure 19. Detail SDO Output Schematic of the AD5204 All digital pins are protected with a series input resistor and parallel Zener ESD structure shown in Figure 20. Applies to digital pins CS, SDI, SDO, PR, SHDN, CLK 340k LOGIC VSS Figure 20. ESD Protection of Digital Pins A, B, W VSS Figure 21. ESD Protection of Resistor Terminals V+ DUT VMS A B W V+ = VDD 1LSB = V+/256 Figure 22. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL) NO CONNECT IW DUT VMS A B W Figure 23. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) IMS VW IW = 1V/RNOMINAL DUT VMS A B W V+ IW RW = –––––––––––––––––––––––––– VW2–[VW1 + IW (RAWII RBW)] WHERE VW1 = VMS WHEN IW = 0 AND VW2 = VMS WHEN IW = 1/R V+ VDD Figure 24. Wiper Resistance Test Circuit PSRR (dB) = 20 LOG ( ––––– ) PSS (%/%) = ––––––– VMS VDD VMS% VDD% V+ = VDD ± 10% VDD VA ~ V+ VMS A B W Figure 25. Power Supply Sensitivity Test Circuit (PSS, PSRR) AB VIN OP279 +5V VOUT DUT W OFFSET GND + OFFSET BIAS Figure 26. Inverting Programmable Gain Test Circuit AB VIN OP279 +5V VOUT DUT W OFFSET GND OFFSET BIAS Figure 27. Noninverting Programmable Gain Test Circuit +15V –15V A B VIN 2.5V OP42 VOUT DUT W OFFSET GND + Figure 28. Gain vs. Frequency Test Circuit ISW VSS TO VDD RSW = 0.1V ISW CODE = ØØH 0.1V DUT B W + Figure 29. Incremental ON Resistance Test Circuit |
类似零件编号 - AD5204BRU10 |
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类似说明 - AD5204BRU10 |
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