REV. F

–7–

AD420

APPLICATIONS

CURRENT OUTPUT

The AD420 can provide 4 mA–20 mA, 0 mA–20 mA, or 0 mA–

24 mA output without any active external components. Filter

capacitors C1 and C2 can be any type of low cost ceramic ca-

pacitors. To meet the specified full-scale settling time of 3 ms,

low dielectric absorption capacitors (NPO) are required. Suit-

able values are C1 = 0.01

µF and C2 = 0.01 µF.

5

2

4

6

7

8

9

C1

C2

20

21

23

REF

OUT

REF

IN

15

14

11

GND

RANGE

SELECT 1

RANGE

SELECT 2

CLEAR

LATCH

CLOCK

DATA IN

AD420

18

0.1 F

0.1 F

Figure 5. Standard Configuration

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads connect a

0.01

µF capacitor between I

This will ensure stability of the AD420 with loads beyond

50 mH. There is no maximum capacitance limit. The capacitive

component of the load may cause slower settling, though this

may be masked by the settling time of the AD420. A pro-

grammed change in the current may cause a back EMF voltage

on the output that may exceed the compliance of the AD420.

To prevent this voltage from exceeding the supply rails connect

VOLTAGE-MODE OUTPUT

Since the AD420 is a single supply device, it is necessary to add

tion of bipolar output voltage ranges as shown in Figure 6.

6

7

8

9

C1

C2

20

21

23

R2

REF

OUT

REF

IN

15

14

11

GND

RANGE

SELECT 1

RANGE

SELECT 2

CLEAR

LATCH

CLOCK

DATA IN

AD420

17

4

5

R1

R3

0.1 F

0.1 F

2

Figure 6.

Table IV. Buffer Amplifier Configuration

R1

R2

R3

Open

Open

0

0 V–5 V

Open

R

R

0 V–10 V

R

Open

R

±5 V

R2R

2R

±10 V

Suitable R = 5 k

Ω.

OPTIONAL SPAN AND ZERO TRIM

For those users who would like lower than specified values of

offset and gain error, Figure 7 shows a simple way to trim these

parameters. Care should be taken to select low drift resistors

because they will affect the temperature drift performance of the

DAC.

The adjustment algorithm is iterative. The procedure for trim-

ming the AD420 in the 4 mA–20 mA mode can be accom-

plished as follows:

STEP I . . . OFFSET ADJUST

Load all zeros. Adjust RZERO for 4.00000 mA of output

current.

STEP II . . . GAIN ADJUST

Load all ones. Adjust RSPAN for 19.99976 mA (FS – 1 LSB) of

output current.

Return to STEP I and iterate until convergence is obtained.

6

7

8

9

C1

C2

20

21

500

RSPAN

15

11

GND

RANGE

SELECT1

RANGE

SELECT2

CLEAR

LATCH

CLOCK

DATA IN

AD420

19

4

2

18

5k

RSPAN2

14

23

16

10k

RZERO

5

BOOST

0.1 F

0.1 F

Figure 7. Offset and Gain Adjust

Variation of RZERO between REF OUT (5 V) and GND leads

to an offset adjust range from –1.5 mA to 6 mA, (1.5 mA/V

centered at 1 V).

The 5 k

Ω RSPAN2 resistor is connected in parallel with the

internal 40

Ω sense resistor, which leads to a gain increase of

+0.8%.

As RSPAN is changed to 500

Ω, the voltage on REF IN is

attenuated by the combination of RSPAN and the 30 k

Ω

REF IN input resistance. When added together with RSPAN2

this results in an adjustment range of –0.8% to +0.8%.