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ACE24C1024FM+UH 数据表(PDF) 8 Page - ACE Technology Co., LTD. |
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ACE24C1024FM+UH 数据表(HTML) 8 Page - ACE Technology Co., LTD. |
8 / 16 page ACE24C1024 Two-wire Serial EEPROM VER 1.4 8 Figure 6.Output Acknowledge Device Addressing The 1024K EEPROM device require an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 7). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all the EEPROM devices. The 1024K EEPROM use the three device address bits A2, A1 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hard-wired input pins. The A2,A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The seventh bit (P0) of the device address is a memory page address bit. This memory page address bit is the most significant bit of the data word address that follows. The module package device address word also consists of a mandatory one, zero sequence for the first four most significant bits. The next 3 bits are all zero. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to a standby state. Noise protection: Special internal circuitry place on the SDA and SCL pins prevent small noise spikes from activating the device. Date Security: The ACE24C1024 has a hardware data protect scheme that slows the user to write protect the entire memory when the WP pin is at Vcc. |
类似零件编号 - ACE24C1024FM+UH |
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类似说明 - ACE24C1024FM+UH |
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