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AD2S82AJP 数据表(PDF) 7 Page - Analog Devices |
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AD2S82AJP 数据表(HTML) 7 Page - Analog Devices |
7 / 16 page AD2S81A/AD2S82A REV. B –7– HARMONIC DISTORTION The amount of harmonic distortion allowable on the signal and reference lines is 10%. Square waveforms can be used but the input levels should be adjusted so that the average value is 1.9 V rms. (For example, a square wave should be 1.9 V peak). Triangular and sawtooth waveforms should have a amplitude of 2 V rms. Note: The figure specified of 10% harmonic distortion is for calibration convenience only. POSITION OUTPUT The resolver shaft position is represented at the converter out- put by a natural binary parallel digital word. As the digital position output of the converter passes through the major carries, i.e., all “1s” to all “0s” or the converse, a RIPPLE CLK logic output is initiated indicating that a revolu- tion or a pitch of the input has been completed. The direction of input rotation is indicated by the DIRECTION (DIR) logic output. This direction data is always valid in ad- vance of a RIPPLE CLK pulse and, as it is internally latched, only changing state (1 LSB min change) with a corresponding change in direction. Both the RIPPLE CLK pulse and the DIR data are unaffected by the application of the INHIBIT. The static positional accuracy quoted is the worst case error that can occur over the full operating temperature excluding the effects of offset signals at the INTEGRATOR I/P (which can be trimmed out–see Figures 1a and 1b), and with the following conditions: input signal amplitudes are within 10% of the nominal; phase shift between signal and reference is less than 10 degrees. These operating conditions are selected primarily to establish a repeatable acceptance test procedure which can be traced to national standards. In practice, the AD2S81A/AD2S82A can be used well outside these operating conditions providing the above points are observed. VELOCITY SIGNAL The tracking converter technique generates an internal signal at the output of the integrator (the INTEGRATOR O/P pin) that is proportional to the rate of change of the input angle. This is a dc analog output referred to as the VELOCITY signal. In many applications it is possible to use the velocity signal of the AD2S81A/AD2S82A to replace a conventional tachogenerator. DC ERROR SIGNAL The signal at the output of the phase-sensitive detector (DEMOD O/P) is the signal to be nulled by the tracking loop and is, there- fore, proportional to the error between the input angle and the output digital angle. This is the dc error of the converter; and as the converter is a type 2 servo loop, it will increase if the output fails to track the input for any reason. It is an indication that the input has exceeded the maximum tracking rate of the converter or, due to some internal malfunction, the converter is unable to reach a null. By connecting two external comparators, this volt- age can be used as a “built-in test.” CONVERTER RESOLUTION (AD2S82A ONLY) Two major areas of the AD2S82A specification can be selected by the user to optimize the total system performance. The reso- lution of the digital output is set by the logic state of the inputs SC1 and SC2 to be 10, 12, 14 or 16 bits and the dynamic char- acteristics of bandwidth and tracking rate are selected by the choice of external components. The choice of the resolution will affect the values of R4 and R6 which scale the inputs to the integrator and the VCO, respec- tively (see the Component Selection section). If the resolution is changed, then new values of R4 and R6 must be switched into the circuit. Note: When changing resolution under dynamic conditions, do it when the BUSY is low, i.e., when Data is not changing. CONVERTER OPERATION When connected in a circuit such as shown in Figure 1, the AD2S81A/AD2S82A operates as a tracking resolver-to-digital converter and forms a type 2 closed loop system. The output will automatically follow the input for speeds up to the selected maximum tracking rate. No convert command is necessary as the conversion is automatically initiated by each LSB increment, or decrement, of the input. Each LSB change of the converter initiates a BUSY pulse. The AD2S81A/AD2S82A is remarkably tolerant of input ampli- tude and frequency variation because the conversion depends only on the ratio of the input signals. Consequently there is no need for accurate, stable oscillator to produce the reference signal. The inclusion of the phase sensitive detector in the con- version loop ensures a high immunity to signals that are not coherent or are in quadrature with the reference signal. SIGNAL CONDITIONING The amplitude of the SINE and COSINE signal inputs should be maintained within 10% of the nominal values if full perfor- mance is required from the velocity signal. The digital position output is relatively insensitive to amplitude variation. Increasing the input signal levels by more than 10% will result in a loss in accuracy due to internal overload. Reduc- ing levels will result in a steady decline in accuracy. With the signal levels at 50% of the correct value, the angular error will increase to an amount equivalent to 1.3 LSB. At this level the repeatability will also degrade to 2 LSB and the dynamic re- sponse will also change, since the dynamic characteristics are proportional to the signal level. The AD2S81A/AD2S82A will not be damaged if the signal inputs are applied to the converter without the power supplies and/or the reference. REFERENCE INPUT The amplitude of the reference signal applied to the converter’s input is not critical, but care should be taken to ensure it is kept within the recommended operating limits. The AD2S81A/AD2S82A will not be damaged if the reference is supplied to the converter without the power supplies and/or the signal inputs. |
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