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AD1864N-J 数据表(PDF) 6 Page - Analog Devices |
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AD1864N-J 数据表(HTML) 6 Page - Analog Devices |
6 / 12 page AD1864 –6– REV. A GROUNDING RECOMMENDATIONS The AD1864 has three ground pins, two labeled AGND and one labeled DGND. AGND, the analog ground pins, are the “high quality” ground references for the device. To minimize distortion and reduce crosstalk between channels, the analog ground pins should be connected together only at the analog common point in the system. As shown in Figure 7, the AGND pins should not be connected at the chip. AD1864 S +V L –V TRIM MSB SJ DL LL DGND AGND OUT V OUT I R F –VS OUT I +VL OUT V TRIM MSB LR CLK DR AGND SJ R F 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VOUT VOUT –ANALOG SUPPLY DIGITAL SUPPLY –DIGITAL SUPPLY ANALOG SUPPLY DIGITAL COMMON Figure 7. Recommended DIP Circuit Schematic The digital ground pin returns ground current from the digital logic portions of the AD1864 circuitry. This pin should be connected to the digital common pin in the system. Other digital logic chips should also be referred to that point. The analog and digital grounds should be connected together at one point in the system, preferably at the power supply. POWER SUPPLIES AND DECOUPLING The AD1864 has four power supply pins. ±V S provides the supply voltages that operate the analog portions of the DAC, including the voltage references, output amplifiers and control amplifiers. The ±V S supplies are designed to operate from ±5 V to ± 12 V. These supplies should be decoupled to analog common using 0.1 µF capacitors. Good engineering practice suggests that the bypass capacitors be placed as close as possible to the package pins. This minimizes the parasitic inductive effects of printed circuit board traces. The ± V L supplies operate the digital portions of the chip, including the input shift registers and the input latching circuitry. These supplies should be bypassed to digital common using 0.1 µF capacitors. ±V L operates with ± 5 V to ± 12 V supplies. In order to assure proper operation of the AD1864, –VS must be the most negative power supply voltage at all times. Though separate positive and negative power supply pins are provided for the analog and digital portions of the AD1864, it is also possible to use the AD1864 in systems featuring a single positive and a single negative power supply. In this case, the +VS and +VL input pins should be connected to the positive power supply. –VS and –VL should be connected to the single negative supply. This feature allows reduction of the cost and complexity of the system power supply. As with most linear circuits, changes in the power supplies will affect the output of the DAC. Analog Devices recommends that well regulated power supplies with less than 1% ripple be incorporated into the design of an audio system. DISTORTION PERFORMANCE AND TESTING The THD+N figure of an audio DAC represents the amount of undesirable signal produced during reconstruction and playback of an audio waveform. The THD+N specification, therefore, provides a direct method to classify and choose an audio DAC for a desired level of performance. Figure 1 illustrates the typical THD+N performance of the AD1864 versus frequency. A load impedance of at least 1.5 k Ω is recommended for best THD+N performance. Analog Devices tests and grades all AD1864s on the basis of THD+N performance. During the distortion test, a high speed digital pattern generator transmits digital data to each channel of the device under test. Eighteen-bit data is latched into the DAC at 352.8 kHz (8 × F S). The test waveform is a 990.5 kHz sine wave with 0 dB, –20 dB and –60 dB amplitudes. A 4096 point FFT calculates total harmonic distortion + noise, signal-to-noise ratio, D-Range and channel separation. No deglitchers or MSB trims are used. OPTIONAL MSB ADJUSTMENT Use of optional adjust circuitry allows residual distortion error to be eliminated. This distortion is especially important when low amplitude signals are being reproduced. The MSB adjust circuitry is shown in Figure 8. The trim pot should be adjusted to produce the lowest distortion using an input signal with a –60 dB amplitude. AD1864 S +V L –V TRIM MSB SJ DL LL DGND AGND OUT V OUT I R F –VS OUT I +VL OUT V TRIM MSB LR CLK DR AGND SJ R F 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 200k Ω 100kΩ 470kΩ 200k Ω 100k Ω 470k Ω Figure 8. Optional DIP THD+N Adjust Circuitry |
类似零件编号 - AD1864N-J |
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类似说明 - AD1864N-J |
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