LC72720YVS

No. A2155-10/18

(2) Synchronization detection method setting (1bit) : BS

BS

Synchronization detection conditions

0

If during 3 blocks, 2 blocks of offset words were detected in the correct order.

1

If the offset words were detected in the correct order in 2 consecutive blocks.

Initial value : BS = 0

(3) Synchronization and RAM address reset (1bit) : SYR

SYR

Synchronization detection circuit

RAM

0

Normal operation (reset cleared)

Normal write (See the description of the OWE bit)

1

Forced to the unsynchronized state

(synchronization reset)

After the reset is cleared, start writing from the data prior

to the establishment of synchronization, i.e. the data in

backward protection.

Initial value : SYR = 0

1. To apply a synchronization reset, set SYR to 1 temporarily using CCB, and then set it back to 0 again using CCB.

The circuit will start synchronization capture operation at the point SYR is set to 0.

2. The SYR pin (pin30) also provides an identical reset control operation. Applications can use either method.

However, the control method that is not used must be set to 0 at all times.

Any pulse with a width of over 250 ns will suffice.

3. A reset must be applied immediately after the reception channel is changed.

If a reset is not applied, reception data from the previous channel may remain in on-chip memory.

4. Data read out after a synchronization reset is read out starting with the backward protection block data preceding

the establishment of synchronization.

(4) RAM write control (1bit) : OWE

OWE

RAM write conditions

0

Only data for which synchronization had been established is written.

1

Data for which synchronization not has been established (unsynchronized data) is also

written. (However, this applies when SYR = 0.)

Initial value : OWE = 0

(5) Error correction method setting (5bits) : EC0 to EC4

Initial values : EC0 = 0, EC1 = 1, EC2 = 0, EC3 = 0, EC4 = 1

of bits corrected is set to 0 (error detection only). With these settings, data will be output for blocks with no errors.

2. As opposed to soft-decision B, the soft-decision A setting suppresses soft decision error correction.

E

C

0

E

C

1

E

C

2

Number of bits corrected

0

0

0

0 (error detection only)

1

0

0

1 or fewer bits

0

1

0

2 or fewer bits

1

1

0

3 or fewer bits

0

0

1

4 or fewer bits

1

0

1

5 or fewer bits

0

1

1

Illegal value

1

1

1

Illegal value

E

C

3

E

C

4

Soft-decision setting

00

MODE0 Hard decision

10

MODE1 Soft decision A

01

MODE2 Soft decision B

1

1

Illegal value