8

Am29F160D

Am29F160D_00_D10 April 23, 2010

D A TA SH EE T

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The register is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control levels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1.

Am29F160D Device Bus Operations

Legend:

Notes:

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 operate in the byte or word configura-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and control-

led by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configuration, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

control and selects the device. OE# is the output control

and gates array data to the output pins. WE# should re-

The internal state machine is set for reading array

data upon device power-up, or after a hardware reset.

This ensures that no spurious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See Reading Array Data‚ on page 18 for more informa-

tion. Refer to the AC Read Operations table for timing

specifications and to the Read Operations Timings di-

Operation

CE#

OE#

WE#

WP#

RESET#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

BYTE#

Read

L

L

H

X

H

DQ8–DQ14 = High-Z,

DQ15 = A-1

Write

L

H

L

(Note 3)

H

Standby

0.5 V

X

X

(Note 4)

0.5 V

X

High-Z

High-Z

High-Z

Output Disable

L

H

H

X

H

X

High-Z

High-Z

High-Z

Reset

X

X

X

X

L

X

High-Z

High-Z

High-Z

Sector Protect

(Note 2)

L

H

L

X

Sector Address,

A6 = L, A1 = H,

A0 = L

X

X

Sector Unprotect

(Note 2)

L

H

L

X

Sector Address,

A6 = H, A1 = H,

A0 = L

X

X

Temporary Sector

Unprotect

X

X

X

(Note 3)

High-Z