CXA3266Q datasheet(7/60 Pages) SONY

部件名	CXA3266Q

功能描述	PLL IC for LCD Monitor/Projector

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制造商	SONY [Sony Corporation]

网页	http://www.sony.co.jp

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CXA3266Q

External VCO input.

Programmable counter test input

(controlled by a control register).

When using the VCO TTL input, open

the Pin 3 VCOH and Pin 4 VCOL

PECL inputs.

Phase detector disable signal.

Active high. When this pin is high, the

phase detector output is held. This pin

goes to high level when open.

(See the HOLD Timing Chart.)

Sync input.

When using the SYNC TTL input,

open the Pin 7 SYNCH and Pin 8

SYNCL PECL inputs.

The sync signal can be switched

between positive/negative polarity by

an internal register.

Control signal (enable) for setting the

internal registers.

When SENABLE is low, registers can

be written; when high, registers can be

read.

(See the Control Register Table and

Control Timing Chart.)

Control signal (clock) for setting the

internal registers.

When SENABLE is low, SDATA is

loaded to the registers at the rising

edge of SCLK.

When SENABLE is high, the register

contents are output from SEROUT at

the falling edge of SCLK.

(See the Control Register Table and

Control Timing Chart.)

Control signal (data) for setting the

internal registers.

(See the Control Register Table and

Control Timing Chart.)

Programmable counter test input.

This pin is normally open status and

high. Register contents can be loaded

immediately to programmable counter

by setting TLOAD low during the

programmable counter test mode.

5

6

9

10

11

12

13

VCO

HOLD

SYNC

SENABLE

SCLK

SDATA

TLOAD

TTL

I

5

6

9

10

12

13

1.5V

IOVCC

IOGND

11

192

40k

No.

Symbol

I/O

Reference

voltage level

Equivalent circuit

Description

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