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NBVSPA013LN1TAG 数据表(PDF) 2 Page - ON Semiconductor |
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NBVSPA013LN1TAG 数据表(HTML) 2 Page - ON Semiconductor |
2 / 7 page NBVSPA013 http://onsemi.com 2 Figure 1. Simplified Logic Diagram PLL Clock Multiplier Crystal GND OE VC CLK CLK VDD 65 4 12 3 LVDS OE VC GND CLK VDD CLK 1 2 3 6 5 4 Figure 2. Pin Connections (Top View) Table 1. PIN DESCRIPTION Pin No. Symbol I/O Description 1 VC (Note 1) Analog Input Analog control voltage input pin that adjusts output oscillation frequency. f0 =VC = 1.25 V 2 OE LVTTL/LVCMOS Control Input Output Enable Pin. When left floating pin defaults to logic HIGH and output is active. See OE pin description Table 2. 3 GND Power Supply Ground at 0 V. Electrical and Case Ground. 4 CLK LVDS Output Non−Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 5 CLK LVDS Output Inverted Clock Output. Typically loaded with 100 W receiver termination resistor across differential pair. 6 VDD Power Supply Positive Power Supply Voltage. Voltage should not exceed 2.5 V ±5%. 1. Control voltage has a positive slope with a typical linearity of ±10%; VC = 1.25 V ± 1 V. Table 2. OUTPUT ENABLE TRI−STATE FUNCTION OE Pin Output Pins Open Active HIGH Level Active LOW Level High Z Table 3. ATTRIBUTES Characteristic Value Input Default State Resistor 170 kW ESD Protection Human Body Model Machine Model 2 kV 200 V Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test |
类似零件编号 - NBVSPA013LN1TAG |
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