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MC74HC174ANG 数据表(PDF) 3 Page - ON Semiconductor

部件名 MC74HC174ANG
功能描述  Hex D Flip-Flop with Common Clock and Reset
Download  10 Pages
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制造商  ONSEMI [ON Semiconductor]
网页  http://www.onsemi.com
标志 ONSEMI - ON Semiconductor

MC74HC174ANG 数据表(HTML) 3 Page - ON Semiconductor

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MC74HC174A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
(Referenced to GND)
*0.5 to )7.0
V
VIN
DC Input Voltage
(Referenced to GND)
*1.5 to VCC )1.5
V
VOUT
DC Output Voltage
(Referenced to GND) (Note 1)
*0.5 to VCC )0.5
V
IIN
DC Input Current, per Pin
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$50
mA
TSTG
Storage Temperature Range
*65 to )150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
PDIP, SOIC, TSSOP
260
_C
TJ
Junction Temperature Under Bias
)150
_C
qJA
Thermal Resistance
PDIP
SOIC
TSSOP
78
112
148
_C/W
PD
Power Dissipation in Still Air at 85_C
PDIP
SOIC
TSSOP
750
500
450
mW
MSL
Moisture Sensitivity
Level 1
FR
Flammability Rating
Oxygen Index: 30% − 35%
UL 94 V−0 @ 0.125 in.
VESD
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u100
u500
V
ILATCHUP Latchup Performance
Above VCC and Below GND at 85_C (Note 5)
$300
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage
(Referenced to GND)
2.0
6.0
V
VIN,
VOUT
DC Input Voltage, Output Voltage
(Referenced to GND) (Note 6)
0
VCC
V
TA
Operating Temperature, All Package Types
*55
)125
_C
tr, tf
CLOCK Input Rise and Fall Time (Figure 4)
VCC = 2.0 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
0
1000
700
500
400
ns
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.


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