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CXA1977R

12. Digital output (D0 to D9)

Output pin of D9 (MSB) to D0 (LSB).

TTL output.

Output data polarity inversion is executed by means of MINV and LINV signals, and they can output in

binary, 1'S complement and 2'S complement.

Also, by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart. For

the timing, refer to the Timing Chart.

13. Overflow output (OVER)

When the input signal exceeds VREFT, overflow signal is output.

MINV and LINV have no effect on this pin.

Also by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

For the timing, refer to the Timing Chart.

14. Underflow output (UNDER)

When the input signal turns below VREFB, underflow signal is output.

MINV and LINV have no effect on this pin.

Also by turning ENABLE signal to high level, the output can be turned into high impedance output.

However, when the output level is for high impedance output or is in power save mode, the voltage of 3.6V

or more must not be applied to prevent the distruction of IC.

For correspondence with analog input voltage and output data code, refer to the Output Formula Chart.

For the timing, refer to the Timing Chart.