TPIC5323L

3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

1

POST OFFICE BOX 655303

description

The TPIC5323L is a monolithic gate-protected

logic-level power DMOS array that consists of

three electrically isolated independent N-channel

provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series

with a 1.5-k

Ω resistor.

The TPIC5323L is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized

for operation over the case temperature of – 40

°C to 125°C.

schematic

GATE1

DRAIN1

9

5

Q1

Q2

Q3

6, 7

1, 2

12, 13

Z1

Z2

Z3

SOURCE2

DRAIN2

DRAIN3

GATE2

GATE3

D1

D2

D3

SOURCE1

14, 15

16

GND

8

3, 4

10, 11

SOURCE3

ZC2b

ZC2a

ZC1b

ZC1a

ZC3b

ZC3a

NOTE A: For correct operation, no terminal can be taken below GND.

Copyright

© 1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

DRAIN2

DRAIN2

SOURCE2

SOURCE2

GATE2

DRAIN3

DRAIN3

GND

GATE1

SOURCE1

SOURCE1

DRAIN1

DRAIN1

SOURCE3

SOURCE3

GATE3

D PACKAGE

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