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74LVCH245APW-Q100 数据表(PDF) 3 Page - NXP Semiconductors |
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74LVCH245APW-Q100 数据表(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVC_LVCH245A_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved. Product data sheet Rev. 1 — 3 September 2012 3 of 16 NXP Semiconductors 74LVC_LVCH245A_Q100 Octal bus transceiver; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and TSSOP20 Fig 4. Pin configuration for DHVQFN20 74LVC245A-Q100 74LVCH245A-Q100 DIR VCC A0 OE A1 B0 A2 B1 A3 B2 A4 B3 A5 B4 A6 B5 A7 B6 GND B7 aaa-003142 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 74LVC245A-Q100 74LVCH245A-Q100 Transparent top view B6 A6 A7 B5 A5 B4 A4 B3 A3 B2 A2 B1 A1 B0 A0 OE 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area GND(1) aaa-003143 Table 2. Pin description Symbol Pin Description DIR 1 direction control A0 to A7 2, 3, 4, 5, 6, 7, 8, 9 data input/output GND 10 ground (0 V) B0 to B7 18, 17, 16, 15, 14, 13, 12, 11 data input/output OE 19 output enable input (active LOW) VCC 20 supply voltage |
类似零件编号 - 74LVCH245APW-Q100 |
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类似说明 - 74LVCH245APW-Q100 |
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