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TPIC5424LNE 数据表(PDF) 4 Page - Texas Instruments |
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TPIC5424LNE 数据表(HTML) 4 Page - Texas Instruments |
4 / 15 page TPIC5424L HBRIDGE LOGICLEVEL POWER DMOS ARRAY SLIS026A − JUNE 1994 − REVISED NOVEMBER 1994 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 resistive-load switching characteristics, TC = 25°C PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td(on) Turn-on delay time 34 68 td(off) Turn-off delay time VDD = 25 V, RL = 25 Ω, ten = 10 ns, 40 82 ns tr Rise time VDD = 25 V, tdis = 10 ns, RL = 25 Ω, See Figure 2 ten = 10 ns, 21 42 ns tf Fall time tdis = 10 ns, See Figure 2 25 50 Qg Total gate charge VDS = 48 V, ID = 1 A, VGS = 10 V, 3.9 5 Qgs(th) Threshold gate-to-source charge VDS = 48 V, See Figure 3 ID = 1 A, VGS = 10 V, 0.55 0.8 nC Qgd Gate-to-drain charge See Figure 3 2.5 3.6 nC LD Internal drain inductance 5 nH LS Internal source inductance 5 nH Rg Internal gate resistance 0.25 Ω thermal resistance PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance (see Note 4) DW package 90 °C/W RθJA Junction-to-ambient thermal resistance (see Note 4) NE package All outputs with equal power 60 °C/W RθJP Junction-to-pin thermal resistance DW package All outputs with equal power 30 °C/W RθJP Junction-to-pin thermal resistance NE package 25 °C/W NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink PARAMETER MEASUREMENT INFORMATION VDS = 48 V VGS = 0 TJ = 25°C Z1 and Z3 IRM† 1 0.5 0 − 0.5 − 1 − 1.5 − 2 1.5 − 2.5 Reverse di/dt = 100 A/ µs 25% of IRM† Shaded Area = QRR trr(SD) t − Time − ns 0 50 100 150 200 250 300 350 400 450 500 † IRM = maximum recovery current NOTE A. The above waveform is representative of Z2, Z4, D1, and D2 in shape only. Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode |
类似零件编号 - TPIC5424LNE |
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类似说明 - TPIC5424LNE |
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