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6PAIC23BIPWRG4Q1 数据表(PDF) 23 Page - Texas Instruments

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部件名 6PAIC23BIPWRG4Q1
功能描述  Stereo Audio Codec, 8- to 96-kHz, With Integrated Headphone Amplifier
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

6PAIC23BIPWRG4Q1 数据表(HTML) 23 Page - Texas Instruments

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TLV320AIC23B-Q1
www.ti.com
SGLS240C – MARCH 2004 – REVISED JUNE 2012
3.3.2
Audio Sampling Rates
The TLV320AIC23B-Q1 can operate in master or slave clock mode. In the master mode, the
TLV320AIC23B-Q1 clock and sampling rates are derived from a 12-MHz MCLK signal. This 12-MHz clock
signal is compatible with the USB specification. The TLV320AIC23B-Q1 can be used directly in a USB
system.
In the slave mode, an appropriate MCLK or crystal frequency and the sample rate control register settings
control the TLV320AIC23B-Q1 clock and sampling rates.
The settings in the sample rate control register control the clock mode and sampling rates.
Table 3-12. Sample Rate Control (Address: 0001000)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
CLKOUT
CLKIN
SR3
SR2
SR1
SR0
BOSR
USB/Normal
Default
0
0
0
1
0
0
0
0
0
CLKIN
Clock input divider
0 = MCLK
1 = MCLK/2
CLKOUT
Clock output divider
0 = MCLK
1 = MCLK/2
SR[3:0]
Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
BOSR
Base oversampling rate
USB mode:
0 = 250 fs
1 = 272 fs
Normal mode:
0 = 256 fs
1 = 384 fs
USB/Normal
Clock mode select:
0 = Normal
1 = USB
X
Reserved
The clock circuit of the AIC23B has two internal dividers. The first, controlled by CLKIN, applies to the
sampling-rate generator of the codec. The second, controlled by CLKOUT, applies only to the CLKOUT
terminal. By setting CLKIN to 1, the entire codec is clocked with half the frequency, effectively dividing the
resulting sampling rates by two. The following sampling-rate tables are based on CLKIN = MCLK.
3.3.2.1
USB-Mode Sampling Rates (MCLK = 12 MHz)
In the USB mode, the following ADC and DAC sampling rates are available:
SAMPLING RATE(1)
SAMPLING-RATE CONTROL SETTINGS
FILTER TYPE
ADC (kHz)
DAC (kHz)
SR3
SR2
SR1
SR0
BOSR
96
96
3
0
1
1
1
0
88.2
88.2
2
1
1
1
1
1
48
48
0
0
0
0
0
0
44.1
44.1
1
1
0
0
0
1
32
32
0
0
1
1
0
0
8.021
8.021
1
1
0
1
1
1
8
8
0
0
0
1
1
0
48
8
0
0
0
0
1
0
44.1
8.021
1
1
0
0
1
1
8
48
0
0
0
1
0
0
8.021
44.1
1
1
0
1
0
1
(1)
The sampling rates are derived from the 12-MHz master clock. The available oversampling rates do not produce exactly 8-kHz, 44.1-
kHz, and 88.2-kHz sampling rates, but 8.021 kHz, 44.117 kHz, and 88.235 kHz, respectively. See Figure 3-9 through Figure 3-26 for
filter responses.
3.3.2.2
Normal-Mode Sampling Rates
In normal mode, the following ADC and DAC sampling rates, depending on the MCLK frequency, are
available:
Copyright © 2004–2012, Texas Instruments Incorporated
How to Use the TLV320AIC23B-Q1
23
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Product Folder Link(s): TLV320AIC23B-Q1


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