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ADC1004S030 数据表(PDF) 7 Page - Integrated Device Technology |
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ADC1004S030 数据表(HTML) 7 Page - Integrated Device Technology |
7 / 18 page ADC1004S030_040_050_4 © IDT 2012. All rights reserved. Product data sheet Rev. 04 — 2 July 2012 7 of 18 Integrated Device Technology ADC1004S030/040/050 Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Rlad ladder resistance - 245 - TCRlad ladder resistor temperature coefficient - 456 - m /K Voffset offset voltage BOTTOM; VRT VRB = 2.37 [2] - 175 - mV TOP; VRT VRB = 2.37 [2] - 175 - mV Vi(a)(p-p) peak-to-peak analog input voltage [3] 1.7 2.02 2.55 V Digital outputs D9 to D0 and IR (referenced to OGND) VOL LOW-level output voltage IOL = 1 mA 0 - 0.5 V VOH HIGH-level output voltage IOH = 1 mA VCCO 0.5 - VCCO V IO output current in 3-state mode; 0.5 V < VO < VCCO 20 - +20 A Switching characteristics; Clock input CLK; see Figure 4[1] fclk(max) maximum clock frequency ADC1004S030TS 30 - - MHz ADC1004S040TS 40 - - MHz ADC1004S050TS 50 - - MHz tw(clk)H HIGH clock pulse width full effective bandwidth 8.5 - - ns tw(clk)L LOW clock pulse width full effective bandwidth 5.5 - - ns Analog signal processing Linearity INL integral non-linearity fclk = 40 MHz; ramp input - 0.8 2.0 LSB DNL differential non-linearity fclk = 40 MHz; ramp input - 0.5 0.9 LSB Eoffset offset error middle code; VRB = 1.3 V; VRT = 3.67 V - 1 - LSB EG gain error from device to device; VRB = 1.3 V; VRT = 3.67 V [4] - 0.1 - % Bandwidth (fclk = 40 MHz) B bandwidth full-scale sine wave [5] - 15 - MHz 75 % full-scale sine wave - 20 - MHz small signal at mid-scale; VI = 10 LSB at code 512 - 350 - MHz Table 6. Characteristics …continued VCCA = V3 to V4 = 4.75 V to 5.25 V; VCCD = V11 to V12 and V28 to V27 = 4.75 V to 5.25 V; VCCO = V13 to V14 = 3.0 V to 5.25 V; AGND and DGND shorted together; Tamb = 0 C to +70 C; typical values measured at VCCA = VCCD = 5 V and VCCO = 3.3 V; CL = 15 pF and Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
类似零件编号 - ADC1004S030 |
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类似说明 - ADC1004S030 |
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