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ADC1002S020HL 数据表(PDF) 8 Page - Integrated Device Technology |
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ADC1002S020HL 数据表(HTML) 8 Page - Integrated Device Technology |
8 / 18 page ADC1002S020_3 © IDT 2012. All rights reserved. Product data sheet Rev. 03 — 2 July 2012 8 of 18 Integrated Device Technology ADC1002S020 Single 10 bits ADC, up to 20 MHz [1] In addition to a good layout of the digital and analog ground, it is recommended that the rise and fall times of the clock must not be less than 1 ns. [2] Analog input voltages producing code 0 up to and including code 1023: a) Voffset BOTTOM is the difference between the analog input which produces data equal to 00 and the reference voltage on pin RB (VRB) at Tamb = 25 C. b) Voffset TOP is the difference between the reference voltage on pin RT (VRT) and the analog input which produces data outputs equal to code 1023 at Tamb = 25 C. [3] To ensure the optimum linearity performance of such a converter architecture the lower and upper extremities of the converter reference resistor ladder are connected to pins RB and RT via offset resistors ROB and ROT as shown in Figure 3. a) The current flowing into the resistor ladder is I VRT VRB – ROB RL ROT ++ --------------------------------------- = and the full-scale input range at the converter, to cover code 0 to 1023 is VI RL IL RL ROB RL ROT ++ --------------------------------------- VRT VRB + 0.871 VRT VRB – == = b) Since RL, ROB and ROT have similar behavior with respect to process and temperature variation, the ratio RL ROB RL ROT ++ --------------------------------------- will be kept reasonably constant from device to device. Consequently variation of the output codes at a given input voltage depends mainly on the difference VRT VRB and its variation with temperature and supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the matching between each of them is optimized. [4] The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale input (square wave signal) in order to sample the signal and obtain correct output data. [5] Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent fundamental period. The calculation takes into account all harmonics and noise up to half the clock frequency (Nyquist frequency). Conversion to SIgnal-to-Noise And Distortion (SINAD) ratio: SINAD = ENOB 6.02 + 1.76 dB. [6] Output data acquisition: the output data is available after the maximum delay time of td(o). Timing (fclk = 20 MHz; CL = 20 pF); see Figure4[6] td(s) sampling delay time - - 5 ns th(o) output hold time 5 - - ns td(o) output delay time VDDO = 4.75 V 8 12 15 ns VDDO = 3.15 V 8 17 20 ns 3-state output delay times; see Figure 5 tdZH float to active HIGH delay time - 14 18 ns tdZL float to active LOW delay time - 16 20 ns tdHZ active HIGH to float delay time - 16 20 ns tdLZ active LOW to float delay time - 14 18 ns Standby mode output delay times tTLH LOW to HIGH transition time stand-by - - 200 ns tTHL HIGH to LOW transition time start-up - - 500 ns Table 6. Characteristics …continued VDDA = V7 to V9 = 3.3 V; VDDD = V4 to V3 = V18 to V19 = 3.3 V; VDDO = V20 to V21 = 3.3 V; VSSA, VSSD and VSSO shorted together; Vi(p-p) = 1.83 V; CL = 20 pF; Tamb = 0 C to 70 C; typical values measured at Tamb = 25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit |
类似零件编号 - ADC1002S020HL |
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类似说明 - ADC1002S020HL |
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