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6PAIC3106IRGZRQ1 数据表(PDF) 12 Page - Texas Instruments |
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6PAIC3106IRGZRQ1 数据表(HTML) 12 Page - Texas Instruments |
12 / 102 page T0145-02 WCLK BCLK SDOUT SDIN t (WS) h t (BCLK) H t (DO-BCLK) d t (DO-WS) d t (DI) S t (BCLK) L t (DI) h t (WS) S TLV320AIC3106-Q1 SLAS663A – AUGUST 2009 – REVISED JANUARY 2010 www.ti.com All specifications at 25°C, DVDD = 1.8 V. IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 70 35 ns tL(BCLK) BCLK low period 70 35 ns ts(WS) ADWS/WCLK setup time 10 6 ns th(WS) ADWS/WCLK hold time 10 6 ns td(DO-WS) ADWS/WCLK to DOUT delay time (for LJF Mode only) 50 35 ns td(DO-BCLK) BCLK to DOUT delay time 50 20 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns NOTE: All timing specifications are ensured by design and not tested in production. Figure 3. I2S/LJF/RJF Timing in Slave Mode 12 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TLV320AIC3106-Q1 |
类似零件编号 - 6PAIC3106IRGZRQ1 |
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类似说明 - 6PAIC3106IRGZRQ1 |
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