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MCM69R818AZP8 数据表(PDF) 8 Page - Motorola, Inc |
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MCM69R818AZP8 数据表(HTML) 8 Page - Motorola, Inc |
8 / 20 page MCM69R736A •MCM69R818A 8 MOTOROLA FAST SRAM AC OPERATING CONDITIONS AND CHARACTERISTICS (0 °C ≤ TA ≤ 70°C, Unless Otherwise Noted) Input Pulse Levels 0.25 to 1.25 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Rise/Fall Time 1 V/ns (20% to 80%) . . . . . . . . . . . . . . . . . . . . . . Input Timing Measurement Reference Level 0.75 V . . . . . . . . . . . . . . Output Timing Reference Level 0.75 V . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input Timing Reference Level Differential Cross–Point . . . . . . ZQ for 50 Ω Impedance 250 Ω . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . R θJA Under Test TBD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . READ/WRITE CYCLE TIMING (See Note 1) MCM69R736A–5 MCM69R818A–5 MCM69R736A–6 MCM69R818A–6 MCM69R736A–7 MCM69R818A–7 MCM69R736A–8 MCM69R818A–8 Parameter Symbol Min Max Min Max Min Max Min Max Unit Notes Cycle Time tKHKH 5 — 6 — 7 — 8 — ns Clock High Pulse Width tKHKL 2 — 2.4 — 2.8 — 3.2 — ns Clock Low Pulse Width tKLKH 2 — 2.4 — 2.8 — 3.2 — ns Clock High to Output Low–Z tKHQX1 1 — 1 — 1 — 1 — ns Clock High to Output Valid tKHQV — 2.5 — 3 — 3.5 — 4 ns Clock High to Output Hold tKHQX 0.5 — 0.5 — 0.5 — 0.5 — ns 2 Clock High to Output High–Z tKHQZ — 2.5 — 3 — 3.5 — 4 ns 2, 3 Output Enable Low to Output Low–Z tGLQX 0.5 — 0.5 — 0.5 — 0.5 — ns 2, 3 Output Enable Low to Output Valid tGLQV — 2.5 — 3 — 3.5 — 4 ns Output Enable to Output Hold tGHQX 0.5 — 0.5 — 0.5 — 0.5 — ns Output Enable High to Output High–Z tGHQZ — 2.5 — 3 — 3.5 — 4 ns 2, 3 Setup Times: Address Data In Chip Select Write Enable tAVKH tDVKH tSVKH tWVKH 0.5 — 0.5 — 0.5 — 0.5 — ns Hold Times: Address Data In Chip Select Write Enable tKHAX tKHDX tKHSX tKHWX 1 — 1 — 1 — 1 — ns NOTES: 1. In no case may control input signals (e.g., SS) be operated with pulse widths less than the minimum clock input pulse width specifications (e.g., tKHKL) or at frequencies that exceed the applied K clock frequency. 2. This parameter is sampled, and not 100% tested. 3. Measured at ± 200 mV from steady state. The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time. On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time. TIMING LIMITS DEVICE UNDER TEST ZQ 50 Ω 50 Ω 0.75 V VDDQ/2 Vref 250 Ω Figure 1. Test Load |
类似零件编号 - MCM69R818AZP8 |
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类似说明 - MCM69R818AZP8 |
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