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DRV8823 Datasheet(数据表) 10 Page - Texas Instruments

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部件型号  DRV8823
说明  4-BRIDGE SERIAL INTERFACE MOTOR DRIVER
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DRV8823 Datasheet(HTML) 10 Page - Texas Instruments

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DRV8823
SLVS913D – JANUARY 2009 – REVISED JANUARY 2010
www.ti.com
Protection Circuits
The DRV8823 is fully protected against undervoltage, overcurrent and overtemperature events.
Overcurrent Protection (OCP)
All of the drivers in DRV8823 are protected with an OCP (Over-Current Protection) circuit.
The OCP circuit includes an analog current limit circuit, which acts by removing the gate drive form each output
FET if the current through it exceeds a preset level. This circuit will limit the current to a level that is safe to
prevent damage to the FET.
A digital circuit monitors the analog current limit circuits. If any analog current limit condition exists for longer than
a preset period, all drivers in the device will be disabled.
The device is re-enabled upon the removal and re-application of power at the VM pins.
Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all drivers in the device will be shut down.
The device will remain disabled until the die temperature has fallen to a safe level. After the temperature has
fallen, the device may be re-enabled upon the removal and re-application of power at the VM pin.
Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pins falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled. Operation will resume when VM rises above the UVLO threshold. The indexer logic will
be reset to its initial condition in the event of an undervoltage lockout.
Shoot-Through Current Prevention
The gate drive to each FET in the H-bridge is controlled to prevent any cross-conduction (shoot through current)
during transitions.
Serial Data Transmission
Data transfers consist of sixteen bits of serial data, shifted into the SDATA pin LSB first.
On serial writes to DRV8823, additional clock edges following the final data bit will continue to shift data bits into
the data register; therefore, the last 16 bits presented will be latched and used.
One of two registers is selected by setting bits in an address field in the four upper bits in the serial data
transferred (ADDR in the tables below). One 16-bit register is used to control motor #1 (bridges A & B), and a
second 16-bit register is used to control motor 2 (bridges C & D).
Data can only be transferred into the serial interface if the SCS input pin is active high.
Data is initially clocked in to a temporary holding register. This data is latched into the motor driver on the rising
edge of the SSTB pin. If the SSTB pin is tied high at all times, the data will be latched in after all 16 bits have
been transferred.
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