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CDCLVD1212 数据表(PDF) 6 Page - Texas Instruments |
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CDCLVD1212 数据表(HTML) 6 Page - Texas Instruments |
6 / 20 page CDCLVD1212 SCAS901B – SEPTEMBER 2010 – REVISED JANUARY 2011 www.ti.com TYPICAL CHARACTERISTICS INPUT- AND OUTPUT-CLOCK PHASE NOISES vs FREQUENCY FROM the CARRIER (TA = 25°C and VCC = 2.5V) Input clock RMS jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plot 6 Submit Documentation Feedback Copyright © 2010–2011, Texas Instruments Incorporated Product Folder Link(s): CDCLVD1212 |
类似零件编号 - CDCLVD1212 |
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类似说明 - CDCLVD1212 |
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