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CDCE421ARGER 数据表(PDF) 11 Page - Texas Instruments |
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CDCE421ARGER 数据表(HTML) 11 Page - Texas Instruments |
11 / 27 page Programming Cycle of Six Words and Programming Into EEPROM Example EnterProgrammingSequence Word0 Payload Word1 Payload Word5 Payload StateMachineJump State2 State3 ® StateMachineJump State3 State1 ® Aftereightbits,thepayloaddata aretransferredtotheRAM andbecomeactive Waitforatleast10ms beforeexitingtheEEPROMwritephase forsaveoperation Enter Register Readback Mode 1 1 1 1 1 0 0 1 2 56 57 58 OutputOscillation OutputOscillation EnterReadbackSequence 60thfallingedge switchesbackinto normaloperation EEPROMcontent:firstbitavailable afterfirstfallingedge FetchEEPROM contentwith firstCLK SDATA FOUT CDCE421A www.ti.com..................................................................................................................................................................................................... SCAS873 – APRIL 2009 Figure 3 shows an Enter Programming Mode sequence and how the different words can be written. The addressing of Word0 … Word5 can be seen in bold. After that, the inverted payload for the respective word is clocked in. In this example, this step is followed by a Jump from State 2 →State 3 into Enter EEPROM programming with EEPROM lock. In the EEPROM programming state, it is required to wait at least 10ms for save programming to occur. The last command is a jump from State 3 back to State 1 (normal operation). Then cycle the power and verify that the device is functioning as programmed. Figure 3. Programming Cycle of Six Words and Programming Into EEPROM Similar to the Enter Programming Mode sequence, the Enter Register Readback Mode is written into SDATA. After the command has been issued, the SDATA-input is reconfigured as the clock input. By applying one clock, the EEPROM content is read into the shift registers. Then, by applying further clocks at SDATA, the EEPROM content can be clocked out and observed at FOUT. Additionally, FOUT is reconfigured during this operation, as can be seen in Figure 4. There are 59 bits to be clocked out. With the 61st rising clock edge, the FOUR pin is reconfigured for normal operation. Figure 4. Register Readback Mode Timing Sequence Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): CDCE421A |
类似零件编号 - CDCE421ARGER |
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类似说明 - CDCE421ARGER |
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