CD74HC4017EP

HIGHSPEED CMOS LOGIC DECADE COUNTER/DIVIDER

WITH 10 DECODED OUTPUTS

SCLS550 − DECEMBER 2003

4

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

IO

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

IO

(mA)

VCC

MIN

MAX

MIN

MAX

UNIT

−0.02

2 V

1.9

1.9

CMOS loads

−0.02

4.5 V

4.4

4.4

VOH

VI = VIH or VIL

CMOS loads

−0.02

6 V

5.9

5.9

V

VOH

VI = VIH or VIL

TTL loads

−4

4.5 V

3.98

3.7

V

TTL loads

−5.2

6 V

5.48

5.2

0.02

2 V

0.1

0.1

CMOS loads

0.02

4.5 V

0.1

0.1

VOL

VI = VIH or VIL

CMOS loads

0.02

6 V

0.1

0.1

V

VOL

VI = VIH or VIL

TTL loads

4

4.5 V

0.26

0.4

V

TTL loads

5.2

6 V

0.26

0.4

II

VI = VCC or GND

6 V

±0.1

±1

µA

ICC

VI = VCC or GND

0

6 V

8

160

µA

CIN

CL = 50 pF

10

10

pF

timing requirements over recommended operating free-air temperature range (unless otherwise

noted) (see Figure 1)

PARAMETER

VCC

TA = 25°C

MIN

MAX

UNIT

PARAMETER

VCC

MIN

MAX

MIN

MAX

UNIT

2 V

6

4

fmax Maximum clock frequency

4.5 V

30

20

MHz

fmax Maximum clock frequency

6 V

35

23

MHz

2 V

80

120

CP

4.5 V

16

24

tw

Pulse duration

CP

6 V

14

20

ns

tw

Pulse duration

2 V

80

120

ns

MR

4.5 V

16

24

MR

6 V

14

20

2 V

75

110

CE to CP

4.5 V

15

22

tsu

Setup time

CE to CP

6 V

13

19

ns

tsu

Setup time

2 V

5

5

ns

MR inactive

4.5 V

5

5

MR inactive

6 V

5

5

2 V

0

0

th

Hold time, CE to CP

4.5 V

0

0

ns

th

Hold time, CE to CP

6 V

0

0

ns