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CD74ACT74-Q1 数据表(PDF) 1 Page - Texas Instruments |
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CD74ACT74-Q1 数据表(HTML) 1 Page - Texas Instruments |
1 / 9 page CD74ACT74-Q1 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCHS349A − DECEMBER 2003 − REVISED JANUARY 2008 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Qualified for Automotive Applications D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current − Fanout to 15 F Devices D SCR-Latchup-Resistant CMOS Process and Circuit Design description/ordering information The CD74ACT74 dual positive-edge-triggered device is a D-type flip-flop. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. ORDERING INFORMATION† TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING −40 °C to 125°C SOIC − M Tape and reel CD74ACT74QM96Q1 ACT74Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H LX XL H L LX X H§ H§ H H ↑ HH L H H ↑ LL H H H L X Q0 Q0 § This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2008, Texas Instruments Incorporated 1 2 3 4 5 6 7 14 13 12 11 10 9 8 1CLR 1D 1CLK 1PRE 1Q 1Q GND VCC 2CLR 2D 2CLK 2PRE 2Q 2Q M PACKAGE (TOP VIEW) Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. |
类似零件编号 - CD74ACT74-Q1 |
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类似说明 - CD74ACT74-Q1 |
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