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SL74HC4015 数据表(PDF) 1 Page - System Logic Semiconductor |
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SL74HC4015 数据表(HTML) 1 Page - System Logic Semiconductor |
1 / 6 page SL74HC4015 System Logic Semiconductor SLS Dual 4-Bit Shift Register High-Performance Silicon-Gate CMOS The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of two identical independent 4-stage serial- input/parallel-output registers. Each register has independent Clock and Reset inputs as well as a single serial Data input. “Q” outputs are available from each of the four stages on both registers. All register stages are D-type, master-slave flip-flops. The logic level present at the Data input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplished by a high level on the reset line. • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 µA • High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION SL74HC4015N Plastic SL74HC4015D SOIC TA = -55 ° to 125° C for all packages PIN ASSIGNMENT FUNCTION TABLE Inputs Outputs Clock Data Reset Q0 Qn L L L Qn-1 H L H Qn-1 X L Q0 * Qn * X X H L L * = No Change X = don’t care LOGIC DIAGRAM PIN 16 = VCC PIN 8 = GND |
类似零件编号 - SL74HC4015 |
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类似说明 - SL74HC4015 |
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