1

2

3

6

5

4

SYNC

SCLK

D

IN

V

OUT

GND

AV

/V

DD

REF

DAC5311

DAC6311

DAC7311

www.ti.com

SBAS442A

– AUGUST 2008 – REVISED AUGUST 2011

PIN CONFIGURATION

DCK PACKAGE

SC70-6

(TOP VIEW)

Table 1. PIN DESCRIPTION

PIN

NAME

DESCRIPTION

Level-triggered control input (active low). This is the frame sychronization signal for the input data. When

SYNC goes low, it enables the input shift register and data are transferred in on the falling edges of the

1

SYNC

following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this

edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by

2

SCLK

Serial Clock Input. Data can be transferred at rates up to 50MHz.

Serial Data Input. Data is clocked into the 16-bit input shift register on the falling edge of the serial clock

3

input.

4

Power Supply Input, +1.8V to 5.5V.

5

GND

Ground reference point for all circuitry on the part.

6

Analog output voltage from DAC. The output amplifier has rail-to-rail operation.

Copyright

© 2008–2011, Texas Instruments Incorporated

5