MCM69Q618

4

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations

Symbol

Type

Description

30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50,

81, 83, 85, 98, 100

A0 – A15

Input

Synchronous Address Inputs: These inputs are registered and must

meet setup and hold times.

3, 5, 9, 11, 16, 18, 22, 24, 28, 52, 56, 58,

62, 64, 69, 71, 75, 77

D0 – D17

Input

Synchronous Data Input.

90

E1

Input

Synchronous Chip Enable: Active low for depth expansion.

91

E2

Input

Synchronous Chip Enable: Active high for depth expansion.

92

G

Input

Asynchronous Output Enable Input:

Low — enables output buffers (Qx pins).

High — Qx pins are high impedance.

96

K

Input

Clock: This signal registers the address, data in, and all control signals

except G.

86

PT

Input

Pass–through enable: Synchronous.

4, 6, 10, 12, 15, 17, 21, 23, 27, 53, 57,

59, 63, 65, 68, 70, 74, 76

Q0 – Q17

Output

Synchronous Data Output.

88

W

Input

Synchronous Write.

1, 7, 13, 19, 25, 41, 54, 60, 66, 72, 78, 95

VDD

Supply

+ 3.3 V Power Supply.

2, 8, 14, 20, 26, 55, 61, 67, 73, 79, 94

VSS

Supply

Ground.

29, 31, 33, 35, 37, 39, 43, 45, 47, 49, 51,

80, 82, 84, 87, 89, 93, 97, 99

NC

—

No Connection: There is no connection to the chip.

TRUTH TABLE

Oi

Input at tn Clock

Result from tn + 1 Clock

Notes

Operation

E1

E2

W

PT

Data Input D

Data Output Q

Write and Pass–Through

L

H

L

L

D written to A

D data appears

1

Write/Read

L

H

L

H

D written to A

Q out from A

2

Pass–Through

L

H

H

L

D data

D data appears

3

Read

L

H

H

H

Don’t Care

Q out from A

4

Deselected

X

L

X

X

Don’t Care

Q is high–Z

5

Deselected

H

X

X

X

Don’t Care

Q is high–Z

6

NOTES:

1. Write D to array and output D at Q.

2. Output contents of array to Q then write D to array.

3. Output D at Q. Do not write.

4. Output contents of array to Q. Do not write.

5. No operation.

6. No operation.

K

ADDRESS & CONTROL

VALID

tn

tn + 1

VALID

DATA INPUT D

VALID

DATA OUTPUT Q

PIPELINED READ ACCESS

PASS–THROUGH